Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Reexamination Certificate
1999-12-30
2002-07-02
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
C257S712000, C257S777000, C257S782000, C257S783000, C257S784000, C257S788000, C257S796000
Reexamination Certificate
active
06414385
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a Quad Flat Non-Lead package of semiconductor, and more particularly to a Quad Flat Non-Lead package of semiconductor for improving the heat-dissipating effect of the package.
2. Description of Related Art
In the information explosion of the world nowadays, the integrated circuit has become indispensable in our daily life, regardless of our daily life in food, clothing, lodging, transportation, education, and entertainment, the product assembled by various integrated circuit devices can be found everywhere. Following the evolution of the electronic technology, more sophisticate electronic products with user friendly and complicated functions are continuously progressing and changing. Nevertheless, in order to provide an ongoing convenience and comfortable usage, all the products are heading for the design trend of “Light, Thin, Short, and Small”. In additions, the fabrication process of semiconductor has stepped into the mass production era of 0.18 &mgr;m integrated circuit, and semiconductor products with even higher integration have become at hands easily. As for packaging technology of the back stage, there are many successful cases on the development of precise package structure, i.e. chip scale package (CSP), wafer level package, and Multi-Chip Module(MCM) etc. However, in the respect of the assembly technology of devices, there is also a multi-level printed circuit board (PCB) with even higher density which make the integrated circuit (IC) package even closely and densely dispose on the printed circuit board.
FIG. 1
is a cross-sectional view of a Quad Flat Non-Lead package of a semiconductor according to the prior art and
FIG. 2
is a bottom view corresponding to
FIG. 1
according to the prior art. As shown in FIG.
1
and
FIG. 2
, the structure of the Quad Flat Non-Lead package which has disclosed in the U.S. Pat. No. 5,942,794 (Matsushita, 1999) is constructed on a lead frame and is having a die pad
100
surrounded by a multiple leads
102
. The chip
104
includes an active surface
106
and a back surface
108
. And a plurality of bonding pads
110
for external connections of the chip
104
is set up on the active surface
106
. The chip
104
has its back surface
108
bonded to the die pad
100
by the use of an adhesive
112
while the bonding pads
110
are electrically connected to the leads
102
respectively by the use of bonding wires
114
. What is more, a molding compound
116
normally encapsulates the whole chip
104
, the die pad
100
, the bonding wires
114
, and the top surface
118
a
of the lead
102
. This encapsulating process exposes the bottom surface
118
b
and the side surface
118
c
of the leads
102
for external connections of the whole package structure
120
.
In the conventional structure of the Quad Flat Non-Lead package, the die pad
100
is upward offset in order to make the chip
104
and leads
102
positioned at different level of surfaces. An object of the upward offset of the die pad
100
is that the package can be applied in a relatively large chip in order to increase the packaging density, while the other object is to increase the bondability between the molding compound
116
and the lead frame. However, because of the demand for diminishing the thickness of the package, this conventional package structure is apt to expose the bonding wire
114
while encapsulating, thereby, the yield of the product become lower. Additionally, as the operating speed of the device of the integrated circuit becomes faster and faster nowadays, the heat generated increases accordingly, and since the conventional package structure is unable to provide a better way of heat dissipation, the performance of the electronic device will be affected.
SUMMARY OF THE INVENTION
Therefore, it is the first objective of the present invention to provide a Quad Flat Non-Lead package of semiconductor to improve the heat-dissipating effect of the package.
It is the second objective of the present invention to provide a Quad Flat Non-Lead package capable of increasing the yield.
It is the third objective of the present invention to provide a Quad Flat Non-Lead package to increase the packaging density.
In order to attain the foregoing and other objectives, the present invention provides a Quad Flat Non-Lead package which comprises a chip, a plurality of leads, and a molding compound. The chip is bonded through its active surface to the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pads on the active surface. The leads are disposed at the periphery of the die pad and are electrically connected by a plurality of bonding wires to the bonding pads. Additionally, the molding compound encapsulates the chip, the die pad, the bonding wires, and a portion of the leads so as to make the bottom surface and the side surface of the leads expose in order to become the external connections of the package structure.
According to a preferred embodiment of the present invention, the surface of the die pad excluding the surface that is bonded to the chip can be exposed in order to improve the heat-dissipating effect. Moreover, the back surface of the chip can also be exposed or add a heat spreader to further improve the heat-dissipating effect, and in the mean time to ground the heat spreader in order to improve the electrical performance. Furthermore, a stepped structure can be formed on the bottom surface of the lead by making use of the half-etching or coin method in order to strengthen the adhesive force between the lead and the molding compound.
Furthermore, in order to attain the foregoing and other objectives, the present invention also provides a stacked-chip Quad Flat Non-Lead package that comprises a first chip and a second chip bonded back to back each other. A die pad having an area smaller than that of the first chip is bonded to the active surface of the first chip and is to expose the bonding pad of the first chip. A plurality of leads is disposed at the periphery of the die pad with its bottom surface appears a stepped structure which make each of the leads possess a protruded wire-bonding portion having a relatively thin portion. The leads are electrically connected to the bonding pads of the first chip and the second chip respectively. The bonding pads of the first chip are connected to the top surface of the leads while the bonding pads of the second chip are connected to the protruded wire-bonding portion of the bottom surfaces of the leads. Then, the molding compound is used to encapsulate the first chip, the second chip, the die pad, the bonding wire, and a portion of the surface of the lead while a portion of the bottom surface excluding the protruded wire-bonding portion is exposed.
According to another preferred embodiment of the present invention, the surface of the die pad not bonding to the chip can be exposed in order to increase the heat-dissipating effect. In additions, the active surface of the second chip can also set up a heat spreader to further improve the heat-dissipating performance.
REFERENCES:
patent: 5705851 (1998-01-01), Mostafazadeh et al.
patent: 5904497 (1999-05-01), Akram
patent: 6002181 (1999-12-01), Yamada et al.
patent: 6072239 (2000-06-01), Yoneda et al.
patent: 6177721 (2001-01-01), Suh et al.
patent: 6184580 (2001-02-01), Lin
patent: 6198171 (2001-03-01), Huang et al.
Huang Chien-Ping
Ko Eric
Chaudhuri Olik
Farahani Dana
Siliconware Precisionindustries Co., Ltd.
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