Quad flat no-lead (QFN) chip package assembly apparatus and...

Details Quad flat no-lead (QFN) chip package assembly apparatus and... Quad flat no-lead (QFN) chip package assembly apparatus and...

2006-07-10

2008-07-22

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S123000, C438S127000, C257SE21311, C257SE21499, C257SE21502, C257SE21503, C257SE21506

Reexamination Certificate

active

07402459

ABSTRACT:
In one embodiment the present invention includes a method of fabricating a quad flat no-lead (QFN) chip package. The method includes forming a stamped lead frame; forming a die pad and a lead shrink on one side of the stamped lead frame; mounting a die on the die pad; performing wire bonding; encapsulating the die and the wire bond with a molding compound; removing the stamped lead frame after encapsulating; and sawing the molding compound after the stamped lead frame has been removed. Such method results in improved quality of wire leads, improved lifespan of cutting blades, and reduction of burrs as compared to many existing methods of fabricating QFN chip packages.

REFERENCES:
patent: 6258314 (2001-07-01), Oida et al.
patent: 6395585 (2002-05-01), Brandl
patent: 6608366 (2003-08-01), Fogelson et al.
patent: 6858470 (2005-02-01), Han et al.
patent: 7091596 (2006-08-01), Han et al.

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