Quad flat no-lead package structure and manufacturing method...

Details Quad flat no-lead package structure and manufacturing method... Quad flat no-lead package structure and manufacturing method...

2007-11-06

2007-11-06

Pert, Evan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C257S700000, C257S784000, C257S774000, C257SE23020

Reexamination Certificate

active

10710933

ABSTRACT:
The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.

REFERENCES:
patent: 5793105 (1998-08-01), Pace
patent: 5959846 (1999-09-01), Noguchi et al.
patent: 6261467 (2001-07-01), Giri et al.
patent: 6303978 (2001-10-01), Daniels et al.
patent: 6534879 (2003-03-01), Terui
patent: 6911736 (2005-06-01), Nagarajan
patent: 1156903 (1997-08-01), None

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