Quad data rate RAM

Details Quad data rate RAM Quad data rate RAM

1999-04-26

2002-04-30

Yoo, Do Hyun (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S168000, C365S189040, C365S230030, C365S230040, C365S230050, C365S233100

Reexamination Certificate

active

06381684

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory circuits, and more particularly to a synchronous random access memory (RAM) capable of transferring four data items per clock cycle.
2. Description of the Related Art
Conventional synchronous RAMs have a single data bus for transfer of data, and thus transfer either a read data item or a write data item in every clock cycle. Dual data rate RAMs increase the rate of data transfer to two data items per clock cycle by transferring data on both the rising and falling clock edges. This improves system performance by doubling the data bandwidth without increasing the clock frequency.
An example of a dual data rate RAM is the late-write synchronous static RAM known as Claymore or MSUG-2 developed by a private consortium known as the Motorola Semiconductor Users Group (MSUG). This device was designed for a high performance workstation level 2 cache operating in a point-to-point environment with data rates in excess of 500 MHz. Because the Claymore is a late write RAM with a single data bus, the address and data buses remain idle for one clock cycle during bus turn around (i.e., when a read cycle is followed by a write cycle or vice versa). This results in reduced data bandwidth.
There is a need for a synchronous RAM with higher data bandwidth.
SUMMARY OF THE INVENTION
In accordance with the invention, a synchronous memory circuit includes an address bus for receiving an address, a data-out bus for providing a read data item retrieved from the memory circuit, and a data-in bus for receiving a write data item to be written to the memory circuit, wherein in a clock cycle two write data items are capable of being sequentially transferred into the memory circuit via the data-in bus and two read data items are capable of being sequentially transferred out from the memory circuit via the data-out bus.
In one embodiment, the memory circuit further includes at least four memory blocks, wherein in a clock cycle two read data items are capable of being sequentially read from two of the four memory blocks and two write data items are capable of being sequentially written to the remaining two of the four memory blocks.
In another embodiment, the two read data items are two of at least four read data items sequentially read from at least four respective memory blocks in a read burst operation, and the two write data items are two of at least four write data items sequentially written to at least four respective memory blocks in a write burst operation.
In yet another embodiment, the memory circuit further includes a selection circuit having a control input terminal for receiving a clock signal, wherein in a read burst operation the selection circuit sequentially transfers each of the four read data items to the data-out bus in two consecutive clock cycles.
In another embodiment, the selection circuit includes: a multiplexer having a first input terminal for receiving the clock, a second input terminal for receiving a select signal, and at least four input buses each receiving a respective one of the four read data items; and a tri-state output buffer having an input bus coupled to an output bus of the multiplexer, an output bus connected to the data-out bus, and a control input terminal for receiving a tri-state signal, wherein the output buffer is enabled only during a valid read burst operation.
In another embodiment, the memory circuit further includes: at least four clocked input registers for sequentially providing a burst address received at the address bus and at least one read/write control signal received at an input terminal of the memory circuit to respective four of the at least four memory blocks in two consecutive clock cycles; and at least four pulse generators each coupled to a respective one of the at least four memory blocks, wherein in response to the control signal indicating a write burst operation each pulse generator in turn provides a pulse to a corresponding memory for writing the memory block.
In another embodiment, the memory circuit further includes at least two clocked output registers for receiving a burst of at least four write data items sequentially provided at the data-in bus, and providing each of the four write data items to a respective one of the at least four memory blocks, wherein in response to the pulse provided at each memory block the four write data items are sequentially written to respective four of the at least four memory blocks in two consecutive clock cycles.
In another embodiment, the memory circuit is a dynamic random access memory (DRAM) or a static random access memory (SRAM).
In accordance with the invention a method of accessing a memory circuit includes: (A) initiating a write burst operation to write at least four write data items sequentially to the memory circuit in two consecutive clock cycles, and (B) initiating a read burst operation to read at least four read data items sequentially from the memory circuit in two consecutive clock cycles, wherein the read burst operation and the write burst operation overlap such that in a clock cycle two read data items are sequentially transferred out from the memory circuit and two write data items are sequentially transferred into the memory circuit.
In another embodiment, act (A) further includes: (C) providing an address to the memory circuit, the address representing a write burst address, and (D) asserting a write control signal indicating a write operation. And, act (B) further includes: (E) providing an address to the memory circuit, the address representing a read burst address, and (F) asserting a read control signal indicating a read operation.
In another embodiment, if a second write burst operation is initiated immediately after a first write burst operation the second write burst operation is suppressed while the first write burst operation is carried to completion, and if a second read burst operation is initiated immediately after a first read burst operation the second read burst operation is suppressed while the first read burst operation is carried to completion.
In another embodiment, the method further includes: (G) continuously initiating write burst operations or continuously initiating read burst operations by holding a read/write control signal in the corresponding state while supplying a new addresses for each burst operation.


REFERENCES:
patent: 4882709 (1989-11-01), Wyland
patent: 5126975 (1992-06-01), Handy et al.
patent: 5513327 (1996-04-01), Farmwald et al.
patent: 5515325 (1996-05-01), Wada
patent: 5526320 (1996-06-01), Zagar et al.
patent: 5546344 (1996-08-01), Fawcett
patent: 5568430 (1996-10-01), Ting
patent: 5577236 (1996-11-01), Johnson et al.
patent: 5617362 (1997-04-01), Mori et al.
patent: 5644729 (1997-07-01), Amini et al.
patent: 5652724 (1997-07-01), Manning
patent: 5659696 (1997-08-01), Amini et al.
patent: 5663901 (1997-09-01), Wallace et al.
patent: 5673398 (1997-09-01), Takeda
patent: 5675549 (1997-10-01), Ong et al.
patent: 5699317 (1997-12-01), Sartore et al.
patent: 5787489 (1998-07-01), Pawlowski
patent: 5828606 (1998-10-01), Mick
patent: 5838631 (1998-11-01), Mick
patent: 5841732 (1998-11-01), Mick
patent: 5875151 (1999-02-01), Mick
patent: 5915105 (1999-06-01), Farmwald et al.
patent: 6085300 (2000-07-01), Sunaga et al.
Gibson, Glenn A.,Computer Systems—Concepts and Design,Prentice Hall, Inc., Englewood Cliffs, New Jersey, 1991, pp. 366-369 and 452-493.
Prince, Betty,Semiconductor Memories,Second Edition, (John Wiley & Sons ed., 1991) (1983) pp. 467-472.
“64K×32, 3.3V Synchronous SRAM With Pipelined Outputs and Interleaved/Linear Burst Counter, Preliminary IDT71V632,” Integrated Device Technology, Inc., Product Information, Mar. 1997, 14 pages.
“64K×32, 3.3V Synchronous SRAM With Flow-Through Outputs-Preliminary IDT71V633,” Integrated Device Technology, Inc., Product Information, Apr. 1997, 15 pages.

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