Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2000-03-14
2003-12-02
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S503000, C332S106000, C332S109000
Reexamination Certificate
active
06658583
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a PWM control circuit, microcomputer and electronic equipment.
2. Description of the Related Art
There is known a PWM control circuit for generating such PWM (pulse-width modulation) signals as shown in FIG.
1
A.
A conventional PWM control circuit as shown in
FIG. 1B
comprises a PWM period value setting register
900
, a counter
902
, an edge-point value setting register
904
, comparators
906
.
908
and an Rs flip-flop
909
, for example.
The PWM period value setting register
900
is one that stores a period value for specifying the period TP of a PWM signal Shown in FIG.
1
C. The counter (increment counter)
902
increments a count value based on an operation clock CLK. The edge-point register
904
stores an edge-point setting for specifying a first edge-point (or rising edge)
910
of
FIG. 1C
at which the level of the PWM signal may change from L-level to H-level, for example.
The comparator
906
compares the edge-point value from the edge-point value setting register
904
with the count value from the counter
902
If they are identical with each other, the comparator
906
generates a H-level signal to be outputted toward the terminal S (set terminal) of the RS flip-flop
909
. Thus, the PWM signal will vary from L-level to H-level as shown by the first edge-point (or rising edge)
910
in FIG.
1
C.
The comparator
908
compares the period value from the PWM period value setting register
900
with the count value from the counter
902
. If they are identical with each other, the comparator
908
generates a H-level signal to be outputted toward the terminal R (reset terminal) of the RS flip-flop
909
. Thus, the PWM signal will vary from R-level to L-level as shown by the second edge-point (or falling edge)
912
in FIG.
1
C.
However, it was found that such a PWM control circuit of the prior art raised the following problems when it was included in a microcomputer or ASIC.
For example, there is now assumed a case where the PWM signal outputted from the PWM control circuit is converted into an analog sound signal that is in turn utilized to generate a game sound in a game apparatus or a guide voice in a car navigation system. In such a case, the frequency FP of the PWM signal must be set at 80 KHz or higher to prevent inclusion of any returned noise for generating a high-quality sound. Namely, the period TP of the PWM signal shown in
FIG. 1C
must be set at 1/FP=12.5 &mgr;s or lower.
On the other hand, the frequency FC of the operation clock CLK for actuating the counter
902
of
FIG. 1B
will be restricted in its upper limit due to the performance of the microcomputer or ASIC in which the PWM control circuit is included. For example, a conventional microcomputer designed to aim at reduction of the cost may have its operation clock CLK ranging between 20 MHz and 40 MHz.
For example, if FC is equal to 20 Mz, the resolution (conversion accuracy) of D/A conversion by PWM signal will be equal to about 2
8
from the calculation of FC/FP=(20×10)/(80×10
3
)=250. This corresponds to the resolution of an 8-bit D/A converter. With FC=40 MHz, the resolution of D/A conversion by PWM signal will be equal to about 2
9
from the calculation of FC/FP=(40×10
6
)/(80×10
3
)=500. This corresponds to the resolution of a 9-bit D/A converter. In a microcomputer in which the frequency PC of the operation clock CLK ranges between 20 MHz and 40 MHz, the PWM signal having its resolution of 8-9 bits can only be generated.
In the sound output of a modern electronic equipment such as game apparatus or car navigation system, however, the resolution equal to or more than 10 bits is frequently required. Therefore, the microcomputer in which the frequency PC of the operation clock CLK ranges between 20 MHz and 40 MHz as described cannot meet such a requirement. The microcomputer to be incorporated into such electronic equipment had no other choice but to include an analog D/A converter such as resistance ladder type or serial conversion type. However, such an analog D/A converter has its increased circuit scale and is difficult to design its circuit for realizing the high performance. This leads to various problems in increase of the cost, prolongation of the period required by designing and so on.
SUMMARY OF THE INVENTION
In view of the above-described problems, it is an objective of the present invention to provide a PWM control circuit, microcomputer and electronic equipment which can generate a high-resolution PWM signal through a reduced circuit scale.
To this end, there is provided a PWM (pulse width modulation) control circuit for generating a PWM signal, according to a first aspect of the present invention. This PWM control circuit comprises: a counter for incrementing or decrementing a count value in accordance with a given operation clock; an edge-point value setting register for storing an edge-point value which specifies a first edge-point at which the level of the PWM signal varies; a PWM output circuit for varying the level of the PWM signal at the first edge-point specified by the edge-point value, based on the count value from the counter and the edge-point value from the edge-point value setting register; and a delay value setting register provided on low order side of the edge-point value setting register, for storing a delay value of at least one bit which specifies a delay time of the first edge-point, wherein the PWM output circuit delays the first edge-point by a period which is smaller than one-clock period of the operation clock, in accordance with the delay value stored in the delay value setting register.
According to this aspect of the present invention, the first edge-point is specified by the edge-point value from the edge-point value setting register to generate the PWM signal having its signal level varied at the first edge-point. Furthermore, the first edge-point is delayed by a period smaller than one clock period or the operation clock, according to the delay value from the delay value setting register. Thus, the same resolution as that obtained by increasing the frequency of the operation clock can be obtained without increase of the operation clock frequency. And yet, the resolution of a PWM signal can be improved merely by adding a small-scaled circuit to the conventional PWM control circuit. In other words, the high-resolution PWM signal can be implemented through a small-sized circuit scale.
The delay value Betting register may store one-bit delay value, and the PWM output circuit may delay the first edge-point by one-half clock period of the operation clock, in accordance with the one-bit delay value stored in the delay value setting register. Thus, the resolution of the PWM signal can be improved by one bit merely by adding the one-bit delay value setting register, the circuit for delaying the first edge-point, or the like.
The PWM output circuit may comprise: a comparator for comparing the count value from the counter with the edge-point value from the edge-point value setting register to generate a first signal having a signal level which varies at the first edge-point specified by the edge-point value; a delay circuit for generating a second signal having a signal level which varies at a point delayed from the first edge-point by one-half clock period of the operation clock, based on the first signal and the operation clock; and a multiplexer for selecting the first signal when the one-bit delay value stored in the delay value setting register is at a first level, and for selecting the second signal when the one-bit delay value is at a second level. Thus, the resolution of the PWM signal can be improved by one bit merely by adding a small-scaled circuit. In addition, the PWM signal can be obtained with its increased accuracy since the delay of signal in the delay circuit is based on the operation clock.
The delay value setting register may store an M-bit delay value, and the PWM output circuit
Iida Katsuya
Kudo Makoto
Lee Thomas
Seiko Epson Corporation
Yanchus, III Paul
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