PVT self aligning internal delay line and method of operation

Details PVT self aligning internal delay line and method of operation PVT self aligning internal delay line and method of operation

1997-06-12

1998-06-30

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Signals

365233, G11C 800

Patent

active

057744033

ABSTRACT:
An integrated circuit process, voltage and temperature fluctuation self-aligning internal delay line circuit and method of operation. A PVT related reference signal is compared to a set of reference signals generated from a system voltage. A delay line is varied based upon the comparison results, generating a delayed timing signal related to PVT fluctuations.

REFERENCES:
patent: 3701980 (1972-10-01), Mundy
patent: 4780845 (1988-10-01), Threewitt
patent: 4802136 (1989-01-01), Nose et al.
patent: 5313438 (1994-05-01), Hieda et al.
patent: 5566130 (1996-10-01), Durham et al.

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