PVT compensated auto-calibration scheme for DDR3

Details PVT compensated auto-calibration scheme for DDR3 PVT compensated auto-calibration scheme for DDR3

2011-07-19

2011-07-19

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

C365S193000, C365S194000, C365S233100, C365S233130

Reexamination Certificate

active

07983094

ABSTRACT:
Circuits, methods, and apparatus that provide the calibration of input and output circuits for a high-speed memory interface. Timing errors caused by the fly-by routing of a clock signal provided by the memory interface are calibrated for both read and write paths. This includes adjusting read and write DQS signal timing for each DQ/DQS group, as well as inserting or bypassing registers when timing errors are more than one clock cycle. Timing skew caused by trace and driver mismatches between CK, DQ, and DQS signals are compensated for. One or more of these calibrations may be updated by a tracking routine during device operation.

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