PVD-based metallization methods for fabrication of...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S676000, C257SE21295, C257SE21169, C257SE21161

Reexamination Certificate

active

07745332

ABSTRACT:
Recessed features on a Damascene substrate are filled with metal using plasma PVD. Recessed features having widths of less than about 300 nm, e.g., between about 30-300 nm can be filled with metals (e.g., copper and aluminum), without forming voids. In one approach, the deposition is performed by exposing the substrate to a high-density plasma characterized by high fractional ionization of metal. Under these conditions, the metal is deposited within the recess, without forming large overhang at the opening of the recess. In some embodiments, the metal is deposited within the recess, while diffusion barrier material is simultaneously etched from the field region. In a second approach, recessed features are filled by performing a plurality of profiling cycles, wherein each cycle includes a net etching and a net depositing operation. Etching and depositing parameters are adjusted such that the recessed features are filled without forming overhangs and voids.

REFERENCES:
patent: 4999096 (1991-03-01), Nihei et al.
patent: 5882488 (1999-03-01), Leiphart
patent: 6184137 (2001-02-01), Ding et al.
patent: 6214711 (2001-04-01), Hu
patent: 6398929 (2002-06-01), Chiang et al.
patent: 6605197 (2003-08-01), Ding et al.
patent: 6884329 (2005-04-01), Wang et al.
patent: 6899796 (2005-05-01), Wang et al.
patent: 2002/0153610 (2002-10-01), Stumborg et al.
patent: 2004/0134769 (2004-07-01), Wang et al.
patent: 2004/0188239 (2004-09-01), Robison et al.
patent: 2006/0024939 (2006-02-01), Grunow et al.
patent: 2006/0030151 (2006-02-01), Ding et al.
patent: 2009/0095617 (2009-04-01), Lee et al.
patent: 0878843 (1998-11-01), None
Microelectronic Engineering 33 (1997) pp. 31-38, “Gap filling with PVD processes for copper metallized integrated circuits”.

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