Push-pull FPGA cell

Details Push-pull FPGA cell Push-pull FPGA cell

2008-12-12

2010-11-23

Dinh, Son (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185060, C365S185140

Reexamination Certificate

active

07839681

ABSTRACT:
A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.

REFERENCES:
patent: 5576568 (1996-11-01), Kowshik
patent: 5587603 (1996-12-01), Kowshik
patent: 5625211 (1997-04-01), Kowshik
patent: 5812452 (1998-09-01), Hoang
patent: 6100560 (2000-08-01), Lovett
patent: 6144580 (2000-11-01), Murray
patent: 6222774 (2001-04-01), Tanzawa et al.
patent: 6324102 (2001-11-01), McCollum
patent: 6356478 (2002-03-01), McCollum
patent: 6891769 (2005-05-01), McCollum et al.
patent: 6970383 (2005-11-01), Han et al.
patent: 7120053 (2006-10-01), Atsumi et al.
patent: 7120079 (2006-10-01), McCollum et al.
patent: 7187610 (2007-03-01), McCollum et al.
patent: 7245535 (2007-07-01), McCollum et al.
patent: 7301821 (2007-11-01), Greene et al.
patent: 7368789 (2008-05-01), Dhaoui et al.
patent: 7430137 (2008-09-01), Greene et al.
patent: 7499360 (2009-03-01), McCollum
patent: 2008/0279028 (2008-11-01), McCollum et al.
Co-pending U.S. Appl. No. 11/851,324, filed Sep. 6, 2007 entitled Programmable Memory Cell and Array for Programmable Logic Including Trench Isolation.
Co-pending U.S. Appl. No. 12/177,680, filed Jul. 22, 2008 entitled Split Gate Memory Cell for Programmable Circuit Device.
Co-pending U.S. Appl. No. 12/343,308, filed Dec. 23, 2008 entitled Push-Pull Memory Cell Configured for Simultaneous Programming of N-Channel and P-Channel Non-Volatile Transistors.
Co-pending U.S. Appl. No. 12/371,483, filed Feb. 13, 2009 entitled Array and Control Method for Flash Based FPGA Cell.

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