Purge-based floating body memory

Static information storage and retrieval – Systems using particular element – Semiconductive

Reexamination Certificate

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C365S149000

Reexamination Certificate

active

11151982

ABSTRACT:
In general, in one aspect, the disclosure describes a memory array including a plurality of memory cells arranged in rows and columns. Each memory cell includes a transistor having a floating body capable of storing a charge. A plurality of word lines and purge lines are interconnected to rows of memory cells. A plurality of bit lines are interconnected to columns of memory cells. Driving signals provided via the word lines, the purge lines, and the bit lines can cooperate to alter the charge of the floating body region in one or more of the memory cells.

REFERENCES:
patent: 6621725 (2003-09-01), Ohsawa
patent: 6714436 (2004-03-01), Burnett et al.
patent: 6873539 (2005-03-01), Fazan et al.
patent: 7002842 (2006-02-01), Tang et al.
Ohsawa, Takashi , “Memory Design Using a One-Transistor Gain Cell on SOI”,IEEE Journal of Solid-State Circuits, vol. 37, No. 11, (Nov. 2002), 1510-1522.
Yoshida, Eiji, “A Design of a Capacitorless 1T-DRAM Cell Using Gate-induced Drain Leakage (GIDL) Current for Low-power and High-speed Embedded Memory”,Fujitsu Laboratories Ltd., 4 pages (2003).

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