Punchthrough-triggered ESD protection circuit through gate-coupl

Details Punchthrough-triggered ESD protection circuit through gate-coupl Punchthrough-triggered ESD protection circuit through gate-coupl

1996-07-23

1998-04-21

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257358, 257360, 257361, 257362, 257365, H01L 2362

Patent

active

057420840

ABSTRACT:
A punchthrough-triggered ESD protection circuit which disposes an NMOS transistor at the anode gate of an lateral silicon-controlled rectifier, and a control circuit which provides a gate voltage for the gate of the NMOS transistor. By changing the channel length of the NMOS transistor as well as the gate voltage, the punchthrough voltage of the NMOS transistor is readily adjusted to a predetermined level. When ESD stress is present at the IC pad, the NMOS transistor goes into breakdown because of punchthrough and then triggers on the lateral silicon controlled rectifier. Thus, the trigger voltage of the ESD voltage can be lowered to the punchthrough voltage of the NMOS transistor. Accordingly, the ESD stress at the IC pad is bypassed by the conduction of the ESD protection circuit to allow an internal circuit to be protected from ESD damage.

REFERENCES:
patent: 5182220 (1993-01-01), Ker et al.

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