Punch-through via with conformal barrier liner

Details Punch-through via with conformal barrier liner Punch-through via with conformal barrier liner

1998-08-19

2003-02-18

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S751000, C257S752000, C257S763000

Reexamination Certificate

active

06522013

ABSTRACT:

TECHNICAL FIELD
The present invention relates to manufacturing high density, multi-metal layer semiconductor devices with a reliable interconnection pattern and, more particularly, to manufacturing high density multi-metal layer semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
Escalating demands for high density and performance associated with ultra large scale integration require semiconductor devices with design features of 0.25 microns and under, e.g. 0.18 microns, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching, and deposition techniques.
Conventional methodology for forming patterned metal layers employs a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region or gate electrode. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer, such as spin-on-glass (SOG) or high density plasma (HDP) oxide, is then applied to fill in the gaps, and the surface is planarized, for example, by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to match 0.25 micron design rules and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad for the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the bottom surface of the conductive via is in contact with the metal feature.
A conventional conductive via is illustrated in
FIG. 1
, wherein a first metal feature
100
of a first patterned metal layer is formed on first dielectric layer
110
and exposed by a through-hole
120
etched in second dielectric layer
130
. The first metal feature
100
, which has side surfaces that taper somewhat due to etching, typically has a composite structure comprising a lower metal layer
102
, e.g., titanium (Ti) or tungsten (W), an intermediate or primary conductive layer
104
, e.g., aluminum (Al) or an Al alloy, and an anti-reflective coating (ARC)
106
, such as titanium nitride (TiN).
In accordance with conventional practices, the through-hole
120
is formed so that first metal feature
100
meets the bottom opening, thereby serving as a landing pad for the metal plug filling the through-hole
120
to form the conductive via
160
. Thus, the bottom surface of the conductive via
160
is in contact with the first metal feature
100
. The conductive via
160
electrically connects the first metal feature
100
and a second metal feature
140
, which is part of a second patterned metal layer.
The second metal feature
140
is also typically a composite structure comprising a lower metal layer
142
, a primary conductive layer
144
, and an ARC
146
. The plug filling the through-hole
120
to form the conductive via
160
is typically formed as a composite comprising a first adhesion promoting layer
150
, which is typically a refractory material, such as TiN, Ti—W, or Ti—TiN, and a primary plug filling metal
170
such as W. Metal features
100
and
140
typically comprise metal lines with interwiring spacings therebetween conventionally filled with dielectric material
180
, such as SOG or HDP oxide.
The anti-reflective coating
106
on the first metal feature
100
serves two purposes. First, it improves control over the definition of the photoresist mask through which the patterned metal layer was etched and, hence, the critical dimensions of the first metal feature
100
. Fine control over the critical dimensions of the first metal feature are crucial for the ultimate conductance, resistance, and electromigration resistance of the metal line. For this purpose, it is desirable to for the thickness of the anti-reflective coating to be about 250 Å-550 Å.
Second, the anti-reflective coating
106
serves as an etch stop during the formation of the through-hole to prevent “punch through.” Punch through occurs when the etching of the through-hole
120
cuts through the anti-reflective coating
106
and exposes the Al or Al-alloy primary conductive layer
104
of the first metal feature
100
. Consequently, the Al therein may interact with the tungsten hexafluoride (WF
6
) vapor used to deposit the W and create Aluminum Fluoride (AlF
3
), which is an alloy with higher resistivity and other undesirable properties.
Referring to
FIG. 2
, a first metal feature
200
is formed on a first insulating layer
210
. The first metal feature
200
is part of a first patterned metal layer having a lower metal layer
202
, an intermediate, primary conductive layer
204
, such as Al or an Al alloy, and an upper anti-reflective coating
206
. A through-hole
220
is etched in a second dielectric layer
230
and
280
, having been formed on the first patterned metal layer. The through-hole
220
is etched completely through the anti-reflective coating
206
, resulting in a concavity
222
in the primary conductive layer
204
. Depending on the etching chemistry employed and the solvents used to clean the etched through-hole
220
, a portion of the conductive layer
104
beneath the anti-reflective coating
206
is typically penetrated and undercut as the thickness of the anti-reflective coating
206
is optimized for photolithographic processing. Thus, the concavity
222
can extend beneath non-etched portions of the anti-reflective coating
206
.
The adhesion promoting layer
150
is conventionally deposited by physical vapor deposition (PVD) or other sputtering techniques and does not provide an effective barrier to the interaction of Al with WF
6
during the W deposition. In particular, sputtering TiN does not provide good coverage of the exposed primary conductive layer
104
, especially when the primary conductive layer
104
includes an upper surface with a concave portion undercutting the anti-reflective coating
106
.
One conventional remedial technique is to sputter a rather thick adhesion promoting layer
150
, e.g. about 700 Å to about 800 Å, in an attempt to provide an effective diffusion barrier. However, this approach is disadvantageous because the thick adhesion promoting layer may pinch off the via, leading to voids and increased electrical resistance. Moreover, the resistivity of the adhesion promoting layer
150
is higher, resulting in an increased electrical resistance for the via. Furthermore, sputtering TiN results in a crystalline structure which, even at that thickness, is not entirely effective in reducing diffusion and hence the interaction of Al and WF
6
, since grain boundaries provide a rapid diffusion path.
Variations in the thickness of the second dielectric layer
130
above the first metal feature extend the minimum required time in etching the through-holes in the second dielectric layer
130
. If the etch time is too short, then some through-holes do not reach the metal layer, resulting in a failed electrical connection. On

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