Punch-through prevention in trenched DMOS with poly-silicon laye

Details Punch-through prevention in trenched DMOS with poly-silicon laye Punch-through prevention in trenched DMOS with poly-silicon laye

1997-01-13

1999-11-16

Abraham, Fetsum

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257328, 257332, 257329, 257361, 257362, 257497, 257498, 257499, H01L 2976

Patent

active

059863048

ABSTRACT:
The present invention includes a substrate of a first conductivity type having a top surface including at least two intersecting trenches disposed therein with an insulating layer lining the trenches and a conductive material filling the trenches. The transistor also includes a source region of the first conductivity type extending from the top surface of the substrate adjacent to the trenches toward the substrate. The transistor further has a body region of a second conductivity type of opposite polarity from the first conductivity type, the body region extends from the top surface adjacent from the trenches to the substrate and surrounding the source region. The conductive material filling the trenches including punch-through suppressing blocks covering corners of the cell defined by the intersecting trenches wherein the source region disposed underneath the corners immediately next to the trenches having a lower net concentration of impurities of the first conductivity type than remaining portion of the source region.

REFERENCES:
patent: 5032529 (1991-07-01), Beitman et al.
patent: 5623152 (1997-04-01), Majumdar et al.
patent: 5693569 (1997-12-01), Ueno

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