Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1995-04-13
1996-02-27
Westin, Edward P.
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 95, 326 98, H03K 19096
Patent
active
054951887
ABSTRACT:
A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS circuit which makes only a single transition during evaluation. The circuit is reset to a predetermined state by an input pattern, which is in favor of the faster switching direction of the static CMOS.
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patent: 5121003 (1992-06-01), Williams
patent: 5434520 (1995-07-01), Yetter
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Chen Chih-Liang
Ditlow Gary S.
International Business Machines - Corporation
Sanders Andrew
Tassinari, Jr. Robert P.
Westin Edward P.
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