Pulsed signal transition delay adjusting circuit

Details Pulsed signal transition delay adjusting circuit Pulsed signal transition delay adjusting circuit

2001-05-29

2003-09-02

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S284000

Reexamination Certificate

active

06614278

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to the field of integrated circuits, and more specifically to delay circuits for adjusting delays of pulsed signals.
2. Description of the Related Art
In integrated circuits there is a need to have a delay circuit to provide signal delays for various functions. Delay circuits can be found in internal clock generation for clock signals in dynamic random access memories (DRAMs), and also in power supplies of internal semiconductor chips for controlling the timing of pump voltages.
Referring now to
FIG. 1
, an example of such a delay circuit
100
is described. Circuit
100
is initially taught in the U.S. Pat. No. 5,920,221.
The voltage is input at a node
10
, which is connected to an RC network
11
. RC network
11
includes a resistor
12
, and two directional, oppositely coupled capacitors
18
,
19
. The signal then passes through a signal detector
14
and an inverter circuit
16
. The voltage output on a node
17
is fed back to capacitors
18
,
19
of the RC network
11
.
As the input signal rises and falls, the output signal rises and falls correspondingly, but with a certain delay. The delay in the rise is determined by the values of resistor
12
and capacitor
19
. The delay in the fall is determined by the values of resistor
12
and capacitor
18
.
A limitation of circuit
100
is that the delays in the rise and in the fall cannot be adjusted. That is because the elements that control the amount of rise and fall are part of the circuit.
Another limitation is that there is always an unwanted delay due to a minimum capacitance. This requires further design to avoid.
A problem with circuit
100
is that the feedback scheme permits noise to be coupled. This affects the waveforms, which in turn affects the performance of the overall device.
BRIEF SUMMARY OF THE INVENTION
The present invention overcomes these problems and limitations of the prior art.
Generally, the present invention provides a delay circuit that may be implemented as an integrated circuit. An input node receives an input signal, and a buffer transfers the input signal to a floating node. A detector outputs to an output node an output voltage that has a first level, if the voltage at the floating node is below a threshold, and a second level otherwise. The output voltage is thus a pulsed waveform, which follows the input signal.
The circuit of the invention includes a reference terminal that carries a reference voltage. A capacitor and a switch are coupled between the reference terminal and the floating node. The switch opens and closes responsive to the output voltage. When it opens, it shorts out the capacitor.
The invention offers the advantage that it permits adjusting the delay of the rising transitions and the falling transitions. The adjustment is by changing either the value of the reference voltage, or the capacitance, or both. Moreover, the adjustments are independent of each other.
The invention offers the additional advantage that, by shorting out the capacitor, it eliminates the unwanted delay due to a minimum capacitance. In addition, while the capacitor is shorted out, the coupling noise is eliminated. This makes design easier, along with improving performance.
In an optional embodiment, the circuit includes a phase detector and a delay code generator. These are in a feedback arrangement for continuously adjusting the reference voltages.
These and other embodiments and advantages of the invention will become more readily apparent from the following Detailed Description, which proceeds with reference to the drawings, in which:


REFERENCES:
patent: 5793238 (1998-08-01), Baker
patent: 5920221 (1999-07-01), Shen et al.
patent: 5929681 (1999-07-01), Suzuki
patent: 6150862 (2000-11-01), Vikinski
English translation of Abstract from Japanese Patent No. JP3023710.
English translation of Abstract from Japanese Patent No. JP60137122.
English translation of Abstract from Japanese Patent No. JP62120117.

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