Pulsed flop with embedded logic

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S113000

Reexamination Certificate

active

11304855

ABSTRACT:
In one embodiment, an apparatus comprises a logic circuit, a plurality of passgates, at least one pulse generator, and a plurality of latch elements. The logic circuit has a plurality of inputs, and each of the passgates has an output directly connected to one of the inputs. The pulse generator is configured to generate a pair of control signals to the passgates, and is configured to generate pulses on the pair of control signals to open the passgates. Each of the latch elements is connected to a respective input and is configured to latch the signal on the respective input when passgates are open and to retain the signal on the respective input when the passgates are closed.

REFERENCES:
patent: 4554664 (1985-11-01), Schultz
patent: 4564772 (1986-01-01), Maley et al.
patent: 4628216 (1986-12-01), Mazumder
patent: 5349243 (1994-09-01), McClure
patent: 5426380 (1995-06-01), Rogers
patent: 5557225 (1996-09-01), Denham et al.
patent: 5619511 (1997-04-01), Sugisawa et al.
patent: 5719878 (1998-02-01), Yu et al.
patent: 5784384 (1998-07-01), Maeno
patent: 5996039 (1999-11-01), Lee
patent: 6002284 (1999-12-01), Hill et al.
patent: 6087886 (2000-07-01), Ko
patent: 6346828 (2002-02-01), Rosen et al.
patent: 6348825 (2002-02-01), Galbi et al.
patent: 6629276 (2003-09-01), Hoffman et al.
patent: 6686775 (2004-02-01), Campbell
patent: 6724221 (2004-04-01), Carballo et al.
patent: 6828838 (2004-12-01), Anshumali et al.
patent: 6911845 (2005-06-01), Hossain et al.
patent: 6914453 (2005-07-01), Dhong et al.
patent: 7082560 (2006-07-01), Parulkar et al.
patent: 7109776 (2006-09-01), Tschanz et al.
patent: 7245150 (2007-07-01), Goel et al.
patent: 2005/0268191 (2005-12-01), Shin
patent: 2006/0103443 (2006-05-01), Rhee et al.
U.S. Appl. 11/304,165, filed Dec. 15, 2005, 23 pages.
U.S. Appl. 11/304,854, filed Dec. 15, 2005, 26 pages.
Samuel D. Naffziger, et al., “The Implementation of the Itanium 2 Microprocessor,” IEEE Journal of Solid-State Circuits, vol. 37, No. 11, Nov. 2002, 13 pages.

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