Pulsed dynamic logic environment metric measurement circuit

Details Pulsed dynamic logic environment metric measurement circuit Pulsed dynamic logic environment metric measurement circuit

2007-10-22

2010-02-09

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S046000, C714S724000

Reexamination Certificate

active

07659749

ABSTRACT:
A pulsed dynamic logic environment metric measurement circuit provides self-referenced, low area/cost and low power measurement of circuit environment metrics, such as supply voltage. A cascade of dynamic logic stages is clocked with a pulse having a width substantially independent of an environment metric to which the delay of the dynamic logic stages is sensitive. The number of dynamic logic stages that evaluate within a given pulse provides a direct measure of the pulse width, and thus the value of the circuit metric. The pulse may be generated from a logical exclusive-OR combination of a clock signal provided from two circuit paths that differ in sensitivity to the environment metric to be measured. One circuit path may have a delay substantially determined only by wire delay, which is not substantially sensitive to circuit environment metrics such as power supply voltage.

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Dudek, et al., “A High Resolution CMOS Time-to-Digital Converter Utilizing a Vernier-Based Delay Line”, IEEE Trans. on Solid-State Circuits, vol. 35, No. 2, Feb. 2000.
Restle, et al., “Timing Uncertainty Measurements on the Power5 Microprocessor”, 2004 IEEE ISSC Conference, Jun. 2004.

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