Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1996-12-27
1999-03-09
Santamauro, Jon
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326121, 326 98, H03K 1900, H03K 19096
Patent
active
058806083
ABSTRACT:
The present invention is a novel method of interfacing static logic to domino logic. A static logic block is connected to one input of a domino evaluation tree. The domino evaluation tree operates only during a brief window of time, while an evaluation control block is ON. Since the input to the domino gate only must be stable during this brief window of time, there is no need to latch the output of the static logic.
REFERENCES:
patent: 3601627 (1971-08-01), Booher
patent: 4827160 (1989-05-01), Okano
patent: 4849658 (1989-07-01), Iwamura et al.
patent: 5378942 (1995-01-01), Wu et al.
patent: 5453708 (1995-09-01), Gupta et al.
patent: 5517136 (1996-05-01), Harris et al.
patent: 5638009 (1997-06-01), Sutherland et al.
Donald Draper, et al. "An X86 Microprocessor with Multimedia Extensions," Proceedings From IEEE, Feb. 7, 1997, pp. 172-173.
"Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements", International Solid State Circuits Conference, Feb. 9, 1996, pp. 138-139.
Harris David
Mehta Gaurav G.
Singh S. Deo
Intel Corporation
Le Don Phu
Santamauro Jon
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