Pulsed circuit topology to perform a memory array write...

Details Pulsed circuit topology to perform a memory array write... Pulsed circuit topology to perform a memory array write...

2000-06-30

2003-05-20

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189050, C365S189120

Reexamination Certificate

active

06567337

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is related to copending U.S. patent applications Ser. No. 09/608,857, entitled, “Pulsed Circuit Topology Including a Pulsed, Domino, Flip-Flop,” Ser. No. 09/608,389, entitled, “A Global Clock Self-Timed Circuit with Self-Terminating Precharge for High Frequency Applications,” and Ser. No. 09/608,638, entitled, “Reset First Latching Mechanism for Pulsed Circuit Topologies,” each of which is concurrently filed herewith.
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to high frequency integrated circuits used to perform memory array write operations.
2. Discussion of Related Art
Advances in semiconductor manufacturing technologies have enabled circuit designers to continue to integrate more transistors on a single die. At the same time, computer architecture, and more specifically, processor architecture, continues to focus on shorter and shorter cycle times.
As clock speeds continue to increase (and thus, cycle times continue to decrease) and/or where certain parts of a chip operate at a higher frequency, limitations of conventional logic circuits may prevent such circuits from operating properly at the higher clock speeds. Further, many conventional logic circuits operate using a two-phase clock. For very high operating frequencies, it may not be feasible to generate and distribute a two-phase clock due to noise, clock jitter and/or other issues.
Where a pulsed clock is used instead of a conventional two-phase clock, the logic may be more susceptible to functional errors due to race conditions making such circuits more difficult for design engineers to work with.


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