Pulse write driver circuit

Details Pulse write driver circuit Pulse write driver circuit

1993-12-29

1995-02-28

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

365190, 365194, 36518905, 36518908, 326 82, 326104, G11C 700

Patent

active

053943635

ABSTRACT:
A pulse write driver circuit comprising a first NAND gate for inputting a write enable signal and a data input transfer negative signal, a second NAND gate for inputting the write enable signal and a data input transfer positive signal, an odd number of first inverters for sequentially inverting an output signal from the first NAND gate, a first NOR gate for inputting the output signal from the first NAND gate and an output signal from the first inverters, an odd number of second inverters for sequentially inverting an output signal from the second NAND gate, a second NOR gate for inputting the output signal from the second NAND gate and an output signal from the second inverters, an odd number of third inverters for sequentially inverting the write enable signal, a third NOR gate for inputting the write enable signal and an output signal from the third inverters, a fourth NOR gate for inputting output signals from the first to third NOR gates, and a fourth inverter for inverting an output signal from the fourth NOR gate. Also, the pulse write driver circuit comprises first and second NMOS transistors and first and second PMOS transistors.

REFERENCES:
patent: 5121356 (1992-06-01), Park et al.
patent: 5278788 (1994-01-01), Nomura

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