Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
1999-10-28
2001-03-13
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S099000, C327S261000, C327S276000
Reexamination Certificate
active
06201414
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to pulse width modulation and more particularly to a logic design which significantly reduces the number of required logic blocks and the size of the chip containing the pulse width modulation logic.
Typically, for pulse width modulation using digit delay, a logic design with numerous logic blocks such as D flip flops are needed. Referring to
FIG. 1
, there is shown a prior art logic diagram which utilizes four positive edge triggered D flip flops to delay a signal for 4 mclock cycles. Referring to
FIG. 2
, there are shown signals of a clock C, an input signal D, and output signals D
1
, D
2
, D
3
, and D
4
. Referring to both
FIGS. 1 and 2
, the input signal D is applied to DF
1
which will be held until the rising edge t
1
of the clock C sends out the input D to the output D
1
. As a result, input D is delayed by T′. D
1
reaches DF
2
slightly after the rising edge t
1
of clock C reaches DF
2
. Therefore, D
1
will be sent to the next flip flop DF
3
on the rising edge t
2
of the clock C. As a result, the delay created by DF
2
is T which is equal to one cycle of clock C. In the same manner the delay created by DF
3
and DF
4
each is equal to one period T of the clock C.
The logic block diagram of
FIG. 1
is a typical delay logic. Using this logic design requires a number of flip flops equal to the required number of delays. For example, if 32T delays are required, 32 flip flops will be needed. This design can become quite large if a delay of for example up to 64T is needed for 32 lines. This means that each line has to have 64 flip flops resulting in total 32×64=2068 flip flops.
It is an object of this invention to reduce the number of flip flops and the size and cost of a chip containing pulse width modulation circuit with plurality of delay requirements.
SUMMARY OF THE INVENTION
In accordance with one aspect of this invention, a pulse width modulation circuit comprises a clock dividing block for receiving a system clock and generating a plurality of clocks with different clock cycles. A delaying block receives a signal and delays the signal. The delaying block has a plurality of delaying elements. Each one of the plurality of delaying elements receives one of the plurality of clocks. The delaying block receives a delay data and responds to the delay data for selecting a number of the plurality of clocks based on the delay data and activates the respective delaying elements. The delaying block is so constructed and arranged to cause the signal to pass through the activated delaying elements and bypass the inactivated delaying elements.
In accordance with another aspect of this invention, a pulse width modulation circuit comprises a clock dividing block for receiving a system clock and generating a plurality of clocks with different clock cycles. A plurality of delaying blocks receive a signal and delay the signal according to a plurality of data. Each of the delaying block has a plurality of delaying elements. Each of the plurality of delaying elements of each delaying blocks receives one of the plurality of clocks. Each of the plurality of delaying blocks receives one of the plurality of delay data and responds to the respective delay data for selecting a number of the plurality of clocks based on the delay data and activates the respective delaying elements. Each of the delaying blocks being so constructed and arranged to cause the signal to pass through the respective activated delaying elements and bypass the respective inactivated delaying elements.
REFERENCES:
patent: 5973525 (1999-10-01), Fujii
patent: 6150847 (2000-11-01), Lu
Fariba Rad
Tokar Michael
Tran Anh Q.
Xerox Corporation
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