Pulse triggered static flip-flop having scan test

Details Pulse triggered static flip-flop having scan test Pulse triggered static flip-flop having scan test

2005-06-28

2005-06-28

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S113000, C326S098000, C326S095000, C327S200000, C327S208000, C327S218000, C327S211000, C327S213000

Reexamination Certificate

active

06911845

ABSTRACT:
A testable, pulse-triggered static flip-flop. A pulse generator produces a data enable trigger pulse only when a test enable input is low, and a scan test enable trigger pulse only when a test enable input is high. The data enable trigger pulse controls the data input to the flip-flop, while the scan test enable trigger pulse controls the scan test input to the flip-flop. The flip-flop consists of a selection circuit comprised of two latches, each including an inverter and a transmission gate. One latch receives the data input and the other latch receives the scan test input. The data enable trigger pulse controls the transmission gate receiving the data input, and the scan test trigger pulse controls the transmission gate receiving the scan test input. The flip-flop also includes a keeper circuit consisting of a feedback inverter and a static latch.

REFERENCES:
patent: 5189319 (1993-02-01), Fung et al.
patent: 5625303 (1997-04-01), Jamshidi
patent: 6448829 (2002-09-01), Saraf
patent: 6686775 (2004-02-01), Campbell
Harris, Skew-Tolerant Circuit Design, Academic Press, 2001, pp. 51-60, 211-217.

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