Pulse signal transfer unit employing post charge logic

Details Pulse signal transfer unit employing post charge logic Pulse signal transfer unit employing post charge logic

1996-06-27

1998-06-16

Santamauro, Jon

Electronic digital logic circuitry

Interface

Current driving

326 17, 326 83, H03K 190185, H03K 19017

Patent

active

057677000

ABSTRACT:
A pulse signal transfer unit employing post charge logic, comprising a buffering circuit for transferring data with a specified logic value through a data transfer line, a PMOS transistor for supplying a voltage from a voltage source to the data transfer line to initialize a signal on the data transfer line, and a feedback loop circuit for applying the signal on the data transfer line to the PMOS transistor for one of the first and second time periods in response to an external write drive signal to control the PMOS transistor, the second time period being longer than the first time period. According to the present invention, in the case of accessing read data with a relatively narrow pulse width and write data with a relatively wide pulse width, the pulse signal transfer unit initializes the read data at a relatively high speed and the write data at a relatively low speed to provide a signal with a wider pulse width. Therefore, the pulse signal transfer unit is capable of preventing the formation of a current path and enhancing the data processing speed.

REFERENCES:
patent: 4498021 (1985-02-01), Uya
patent: 4598216 (1986-07-01), Lauffer et al.
patent: 4647797 (1987-03-01), Sanwo et al.
patent: 4692637 (1987-09-01), Shoji
patent: 4899066 (1990-02-01), Aikawa et al.
patent: 5539336 (1996-07-01), Nguyen et al.

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