Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2002-08-27
2004-12-07
Tran, Anh Q. (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S080000, C326S081000
Reexamination Certificate
active
06828825
ABSTRACT:
TECHNICAL FIELD
The present invention relates to electrical circuits and more particularly to direct current (DC) to direct current (DC) level shifters.
BACKGROUND OF INVENTION
Voltage level shifter circuits are used in applications where input logic voltage level signals are translated to output signals at higher voltage levels. For example, automotive, electronic data processing, and industrial control applications require high voltage level shifter circuits to drive various peripheral devices. Such circuits are often implemented in application specific integrated circuits (ASICs) or as independently packaged circuits. High voltage level shifter circuits translate a logic level (e.g., 0 to 5 volts) input signal to signals at high voltage levels. The level shifter typically includes a first pull-down transistor cross coupled to the gate of a first pull up transistor via a first node “A”, and a second pull down transistor cross coupled to the gate of a second pull up transistor via a second node. As the data input transitions at the lower voltage level between high logic and low logic, the pull down transistors will transition between pulling one node to ground or logic low causing the other node to be pulled up to a logic high at the higher shifted voltage level. The higher shifted voltage level logic can then be provided as output, for example, through one or more driver circuits.
The design of a low voltage to high voltage level shifter usually involves striking a balance between the strength of pull down transistors and the cross-gate connected pull-up transistors.
FIG. 1
illustrates a conventional level shifter device
10
for converting an input signal from a low voltage V
2
to a high voltage V
1
. The level shifter device
10
includes a level shifting circuit
12
. The level shifting circuit
12
includes a first p-type MOSFET device P
1
with its drain coupled to the drain of a first n-type MOSFET device N
1
through a node “A”. A second p-type MOSFET device P
2
has its drain coupled to the drain of a second n-type MOSFET device N
2
through a node “B”. The node “A” is coupled to the gate of the second p-type MOSFET device P
2
, and the node “B” is coupled to the gate of the first p-type MOSFET device P
1
. An input signal V
IN1
is received at the gate of the second n-type MOSFET device N
2
. The input signal is also received at the gate of the first n-type MOSFET device N
1
through a first inverter
14
. The node “B” provides a level shifted signal to a second inverter
16
, which provides a level shifted output signal. The inverter
14
provides an inverted input signal between V
1
and ground, while the second inverter provides a level shifted output signal between V
2
and V
3
.
The high voltage level shifter
10
translates a logic level (e.g., logic “0”, logic “1”) input signal from signals at a low voltage level range to signals at a high voltage level range. For example, a low level high logic input signal provides a voltage V
2
at the gate of N
2
turning on N
2
and pulling node “B” to ground, which causes a high level high logic output signal V
1
at the output of the inverter
16
. A low level low logic input signal provides a voltage V
2
at the gate of N
1
turning on N
1
and pulling node “A” to ground, which causes P
2
to turn on providing a high level low logic output signal at the output of the inverter
16
. As the input signal transitions between high and low logic states, the transistors N
1
and N
2
turn “ON” and “OFF”, and the transistors P
1
and P
2
turn “OFF” and “ON”, respectively. The logic level shifter device
10
is designed such that P
1
and P
2
are substantially weaker devices than N
1
and N
2
, so that the N devices overdrive the P devices preventing the voltage V
2
from being shorted to ground.
However, since the P devices are substantially weaker than the N devices, the rise time associated with pulling the nodes “A” and “B” high is substantially slower than the fall time associated with pulling the nodes “A” and “B” low.
FIG. 2
illustrates a graph of voltage versus time of various signals associated with the level shifter device
10
of FIG.
1
. The input signal V
IN1
transitions from a logic high to logic low. As the input signal V
IN1
, transitions from a high logic state to a low logic state, the node “B” is pulled to ground very fast with a brief delay associated with providing a logic low at the output V
OUT1
. However, the node “A” takes a substantially longer time to transition from a logic low to a logic high. As the input signal V
IN1
, transitions from a low logic state to a high logic state, the node “A” is pulled to ground very fast with the node “B” taking a substantially longer time to transition from a logic low to a logic high. Therefore, the output is delayed until node “B” rises high enough to trigger the inverter
16
.
A circuit can be provided to mitigate the delay associated with the transition of node “B” from logic high to logic low, which monitors for falling edges on the nodes “A” and “B”, and outputs the logic state that causes that particular node to fall. This implementation provides a level shifter that is edge triggered rather than level triggered. However, there is a period of time (e.g., 60-100 ns) after a transition in which both nodes are low when one of the internal nodes falls, since the other node is slow to rise. Therefore, the voltage on the rising node is not sufficiently high for the logic to detect a falling edge until the period of time after a transition has expired. This results in a dead time where the circuit cannot respond to another edge transition, or recover in time from the previous transition. A new input signal transition provided before the time period will cause the rising node to be pulled low before the data output transition is detected.
SUMMARY OF INVENTION
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to systems and methods for detecting a state change of a level shifter and actively driving the level shifter into the new state to facilitate the recovery of the level shifter. Circuitry is provided for setting up the level shifter for the next transition. The level shifter is provided with an input signal. The present invention monitors the transition of a high logic to low logic of a first internal node and a second internal node associated with the logic transition of the input signal. The first internal node and the second internal node transition between opposing logic levels, such that one internal node is pulled low and the other internal node is pulled high. The monitor determines when a high to low transition is detected at one of the first node and the second node, and then actively drives the other of the first node and the second node to a logic high. During each transition, the monitor is set up to monitor for an edge transition of a high to low transition of the node that is in a logic high state. Therefore, when the transition does occur the node in the logic low state can be pulled up to a logic high quickly to facilitate the recovery of the level shifter.
The following description and the annexed drawings set forth certain illustrative aspects of the invention. These aspects are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
REFERENCES:
patent: 4450371 (1984-05-01), Bismarck
patent: 4980583 (1990-12-01), Dietz
patent: 5539334 (1996-07-01), Clapp, III
Grant David Alexander
Johnson Alan Michael
Brady W. James
Swayze, Jr. W. Daniel
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tran Anh Q.
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