Pulse generator circuitry for timing a low-power memory device

Details Pulse generator circuitry for timing a low-power memory device Pulse generator circuitry for timing a low-power memory device

1999-07-29

2001-05-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Differential sensing

Reexamination Certificate

active

06229746

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior an Italian Patent Application No. MI98-A-001768, filed Jul. 30, 1998, the entire disclosure of which is herein incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated memory circuits and, more particularly, to an integrated static random access memory SRAM.
More specifically, the invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix including a plurality of word lines driven by a row decoder and a plurality of bit lines sensed by sense amplifiers, the matrix including at least a dummy row and a dummy column.
2. Description of the Related Art
As is well known in such a specific technical field, an electronic random access memory device includes a plurality of basic memory cells each comprising six transistors.
The enclosed
FIG. 1
shows an example of a basic six transistors memory cell which is constructed with CMOS technology. The cell
1
shown in
FIG. 1
includes a pair of cross-coupled CMOS inverters
2
and
3
each of which is coupled to a corresponding bit line
4
,
5
of the memory device. The first inverter
2
is coupled to the bit line
4
through a bi-directional access devices
6
while the second inverter
3
is coupled to the adjacent bit line
5
through a second bi-directional access devices
7
.
During the reading and writing phases of the memory cell, a differential voltage must be applied between the bit lines
4
,
5
. In this respect, the cell access to the storage node is called “differential”.
In the reading phase, the swing of bit line amplitude depends on how long the cells have been activated. The voltage difference due to the swing can be kept quite small and can be sensed by the sense amplifier of the memory device. This helps to reduce power consumption.
In the writing phase, the bit line voltage swing should be as large as possible, even a full CMOS level, in order to toggle the cells.
If we consider a RAM memory array or matrix having m rows and n columns, and including six transistors cells, the current consumption can be easily estimated using the following formulas:
Iddr=n*m*Cb*&Dgr;Vr*P
  (1)
for the reading phase, and
Iddw=n*m*Cb*&Dgr;Vw*P
  (2)
for the writing phase;
where: Cb is the bit line capacitance associated to a given cell; &Dgr;Vr is the read voltage bit line swing and &Dgr;Vw is the write voltage bit line swing; P is the probability of a bitline switching during an operation. Usually &Dgr;Vw corresponds to the supply voltage value Vdd.
Some prior art techniques are used to reduce the power dissipation of the memory matrix. Those techniques try to intervene on one or more of the parameters contained in the above formulas.
For instance, a first prior art solution is disclosed by N. Kushiyama et al. in an article entitled “A 295 Mhz CMOS 1M (x256) embedded SRAM using I-directional read/write shared sense amplifiers and self-timed pulsed word-line drivers”, ISSCC Dig. Tech. Papers February 1995, pp. 182-183.
This first solution proposes to reduce power dissipation by reducing the number of cells hung on the bit line using a hierarchical bit line scheme.
A second prior art solution is disclosed by B. Amrutur and H. Horowitz in an article entitled “Technique to reduce power in fast wide memories”, Dig. Tech. Papers, October 1994, Symp. on Low Power Electronics, pp 92-93.
This second solution proposes to reduce power dissipation limiting the read bit line swing by controlling the word line pulse length.
A third prior art solution is disclosed by T. Blalock and R. Jager in an article entitled “A high-speed clamped bit line current-mode sense amplifiers”, IEEE J. Solid State Circuits, vol. 26, No. 4, pp. 542-548, April 1991.
Even this third solution proposes to reduce power dissipation limiting the read bit line swing, by using current-mode sense amplifiers; thus reducing &Dgr;Vr.
A further known solution proposes to limit the write bit line swing to a predetermined value, namely Vdd−Vt, using a NMOS transistors precharge phase.
Moreover, some attempts have already been performed to provide a self-timing control mechanism which could track the size of the memory device as well as process, voltage and temperature variations.
In this respect, a self-timing circuit architecture technique using dummy paths is well known in the art. Such a technique is disclosed by A. L. Silburt et al. in an article entitled, “A 180 Mhz 0.8 &mgr;m BiCMOS Modular Memory Family of DRAMS and Multiport SRAM”, IEEE J.Solid-State Circuits, vol. 28, No. 3, March 1993.
FIG. 2
shows a diagram of this classic self-timing architecture. A memory cells matrix
10
includes a plurality of word lines and a plurality of bit lines. The matrix
10
also includes a dummy-row
11
and a dummy column
12
.
The dummy-row
11
represents a dummy path which has the same capacitive load as a common row of the memory matrix
10
.
The dummy column
12
is formed by the same memory cells forming the columns of the matrix
10
. The capacitance of the bit lines are the same as the dummy bit line represented by the dummy column
12
.
A row decoder
13
is associated to the memory matrix
10
. The dummy column
12
is driven by a dummy row decoder
14
which is a replica of the row decoder
13
portion driving each row of the matrix
10
.
The row decoder
13
and the dummy row decoder
14
are enabled by a signal GO
17
. Since the drive capabilities of the two decoders
13
,
14
are the same and since the capacitative load of the memory rows and the dummy row are the same, the output signal DWL
18
will be tracked exactly as the signal WL
9
.
At the intersection of the dummy row and the dummy column there is an active dummy cell
15
. Such a dummy cell
15
is at least four times stronger than a normal cell of the memory matrix
10
. In other words, the dummy cell
15
has the same capacitive loads of cells in memory matrix
10
, but it is four times stronger and is activated simultaneously with the cells of the memory matrix
10
.
The dummy column
12
discharges a signal dbl
19
four times faster than the other normal bit lines. When the dummy column
12
reaches a specific voltage value, it flips a detector
16
. Such a voltage value is generally set at half the supply voltage Vdd so that the normal bit lines need to discharge a voltage value of Vdd/8 when the dummy bit line reaches the set value.
The signal dbl
19
is used to turn on sense amplifier
24
and to reset the memory device.
A diagram of the amplitudes versus time of the various signals is shown in FIG.
3
.
The above type of timing circuit is advantageous for memory generators used in memories having a variable size since the above circuitry effectively tracks the size of the memory. See for instance the European patent application No. 92830644.8.
The above advantage is independent from from the number of rows and columns in the matrix; the sense amplifier control signal will always arrive at the point wherein the bit line discharge is given by the value Vdd/8. Moreover, since the control circuitry corresponds to the circuitry used in the real datapath, such a control circuitry reacts in the same way to changes in supply voltage, temperature and/or process variables.
Notwithstanding these advantages, the solution disclosed hereinabove has a shortcoming when the desired time to start a reset cycle corresponds to the time in which the sense amplifiers are turned on. A delay period shown in
FIG. 3
as “Treset” 25 is therefore taken before the reset signal presents a falling edge. During this Treset period the bit lines are needlessly discharging and wasting power for no reason.
A reset signal is detected by the dummy dataline simultaneously to the point in time wherein the real bitlines have reached the “tuned” voltage difference value Vdd/8. So, the system must wait the Treset delay while the reset signal propagates through the memory devi

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