Static information storage and retrieval – Addressing – Sync/clocking
Patent
1989-12-12
1993-11-23
Clawson, Jr., Joseph E.
Static information storage and retrieval
Addressing
Sync/clocking
365194, 365195, 365196, 365203, 307265, 307480, 307481, G11C 800
Patent
active
052650642
ABSTRACT:
A circuit which responds to the application of a pulse to its input (6) by generating a pulse at its output (3), the output pulse having a minimum duration T and being extended by the remaining length of the input pulse should the input pulse be still present at the end of the time T, comprises a pair of semiconductor switches (1,2) connecting the output (3) to points (5,4) carrying respective logic levels. The input pulse closes the first switch (1) and also inhibits a gate circuit (9). The resulting logic level on the output (3) closes the second switch (2) after delay by T in a delay circuit (13) and transmission through the gate circuit (9), thereby restoring the original logic level. The instant when this occurs coincides with the presence of the delayed output pulse at the output (14) of the delay circuit and the absence of the pulse at the arrangement input (6). A hold circuit circuit (15) may be provided for holding the logic level currently present at the output (3). The circuit may be used as an equalisation pulse generator for a data path in a semiconductor memory integrated circuit.
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patent: 4843596 (1989-06-01), Miyatake et al.
patent: 4947374 (1990-08-01), Wada et al.
S. Kayano et al., "25-ns 256K.times.1/64K.times.4 CMOS SRAM's", IEEE J. of S.-S. Ckts., vol. SC-21, #5, Oct. 1986, pp. 686-690.
"One CMOS Quad Latch Yields Four One-Shots", M. Blair, EDN, vol. 23, No. 7, pp. 122, 124, Apr. 5, 1978.
Davies Thomas J.
Kunnen, legal representative Henricus J.
O'Connell Cormac
Ontrop Hans
Pfennings, deceased Leonardus C. M. G.
Biren Steven R.
Clawson Jr. Joseph E.
U.S. Philips Corp.
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