Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-01-05
2003-03-11
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S029000, C326S093000, C327S229000
Reexamination Certificate
active
06531894
ABSTRACT:
BACK GROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a drive circuit of the power device, which prevents faulty operations by dv/dt transient signals.
2. Description of the Background Art
FIG. 7
shows a circuit of a semiconductor device
100
, having a conventional drive circuit of the power device. In
FIG. 7
, the circuit has the power source
20
to supply the power source electric potential Vdd against the ground electric potential COM and the half-bridge type power device
19
which includes totem pole-connected power device
17
,
18
, e.g.IGBT (insulating gate bipolar transistor) installed between the power source electric potential Vdd and the ground electric potential COM. Power devices
17
,
18
are reverse and parallel connected to the free-wheel-diode D
1
and D
2
. Moreover, the load (the inductive load, e.g. motors) is connected between a connecting node N
1
of power devices
17
and
18
, and the ground electric potential COM.
The power device
17
is a device switching between the potential at the connecting node N
1
as a standard electric potential and the power source electric potential Vdd supplied by the power source
20
. The power device
17
is called high electric potential side power device. Contrary, the power device
18
is called low electric potential side power device.
Also, the semiconductor device
100
shown in
FIG. 7
, comprises a drive circuit HD of high electric potential side power device and a drive circuit LD of low electric potential side power device, but an explanation about the drive circuit LD of low electric potential side power device is omitted, because the drive circuit LD relates less to the present invention.
Following description explains about a structure of the high electric potential side power device. Two outputs of a pulse generation circuit
1
generating pulsed on-signals and off-signals corresponding to input signals given from a microcomputer provided outside, are connected to gate electrodes of high-voltage N-channel MOS (HNMOS) transistors
2
and
3
which functions as a level shift transistor. Each of drain electrodes of HNMOS transistors
2
and
3
, is connected to one ends of resistances
4
and
5
, moreover these electrodes are connected to inputs of inverter circuits
6
and
7
, too. Also, the ground electric potential COM is given to both of source electrodes of HNMOS transistors
2
and
3
.
Moreover, outputs of inverter circuits
6
and
7
, are connected to set input and reset input of not-inversed-input-typed set-reset-flip-flop circuit
10
. The output Q of said set-reset-flip-flop circuit
10
is connected to a gate electrode of NMOS transistor
12
, and the output Q is connected to an input of the inverter circuit
11
, too. Also, the output of the inverter circuit
11
is connected to the gate electrode of NMOS transistor
13
. The source electrode of NMOS transistor
12
is connected to the drain electrode of NMOS transistor
13
, and that source electrode is connected to the gate electrode of power device
17
, too. High electric potential side power source
16
is provided between the drain electrode of NMOS transistor
12
and the connecting node N
1
.
Other ends of resistances
4
and
5
are connected to the drain electrode of NMOS transister
12
, or, positive potential output of high electric potential side power source
16
. Also, the source electrode of NMOS transistor
13
, or, negative potential output of high electric potential side power source
16
, is connected to anode of diode
8
and that source electrode is connected to anode of diode of a diode
9
, too. The cathode of diode
8
,
9
are connected to the drain electrodes of HNMOS transistor
2
and
3
, respectively.
In said drive circuit HD of high electric potential side power device, dv/dt transient signal which is spread signal of quick transition of voltage, occurs in the line (the line is called line L
1
hereinafter) between the connecting node N
1
and anodes of diode
8
,
9
depending on the switching condition of the half-bridge type power device
19
. Then electric current (the electric current is called dv/dt electric current hereinafter) which is given by the product of the parasitic capacity C and dv/dt transient signal, flows to HNMOS transistors
2
and
3
simultaneously.
Moreover, dv/dt electric current flowing to HNMOS transistors
2
and
3
, has same level of the electric current flowing in ordinary switching, so voltage drops occur at resistance
4
and
5
at the same time. As a result, “H” (positive value in active high) as set input and reset input of set-reset-flip-flop circuit
10
, is simultaneously given to the set-reset-flip-flop circuit
10
. In general, it is impermissible that “H” is simultaneously given to the set input and the reset input of non-inversed-input-type set-reset-flip-flop circuit, and the operation which can't be forecasted, in short, mis-operation is caused.
A protection circuit
26
b
using the logic circuit showing in
FIG. 8
is provided between a level-shift circuit
25
level-shifting on-signals and off-signals of the pulse generation circuit
1
and the set-reset-flip-flop circuit
10
to prevent such mis-operations. A following description explains about the structure of the protection circuit
26
b.
The protection circuit
26
b
has the NAND circuit G
101
which is inputted level-shifted on-signals namely output of the inverter circuit
7
as the first level-shifted signal, and the NAND circuit G
121
which is inputted level-shifted off-signals namely output of the inverter circuit
6
as the second level-shifted signal, and the NAND circuit G
111
which is inputted the first and second level-shifted signals, in the first stage. Series connected inverter circuits G
102
, G
104
are connected to the NAND circuit G
101
, and series connected inverter circuits G
122
, G
124
are connected to the NAND circuit G
121
, and the inverter circuit G
112
is connected to the NAND circuit G
111
. Moreover, outputs of the inverter circuits G
104
, G
112
are inputted to the NOR circuit G
13
, and outputs of the inverter circuits G
124
, G
112
are inputted to the NOR circuit G
14
. These outputs of NOR circuit G
13
, G
14
are set-signals and reset-signals to the set-reset flip-flop circuit
10
.
When dv/dt transient signal flows to the line L
1
, the first and second level-shifted signals are simultaneously inputted to the protection circuit
26
b.
At the time, logic value of signal passing through the NAND circuit G
101
, the inverter circuits G
102
, G
104
and signal passing through the NAND circuit G
121
, the inverter circuits G
122
, G
124
are opposite to the logic value of signal passing through the NAND circuit G
111
and the inverter circuit G
112
, so the NOR circuit G
13
prevents outputting the set signal to the set-reset-flip-flop circuit
10
. The NOR circuit G
14
prevents outputting the reset signal to the set-reset-flip-flop circuit
10
as well as the NOR circuit G
13
. As the result, the structure according to above prevents mis-operations of set-reset-flip-flop circuit
10
.
However there is a gate delay at each logic circuits composing the protection circuit
26
b.
In the case of thinking strictly about the gate delay, the protection circuit
26
b
can not prevent always mis-operations of the set-reset-flip-flop circuit
10
. In other words, the number of logic circuits which signal passing through the NAND circuit G
101
, the inverter circuits G
102
, G
104
and signal passing through the NAND circuit G
121
, the inverter circuits G
122
, G
124
go through, is different from the number of logic circuits which signal passing through the NAND circuit G
111
and the inverter circuit G
112
goes through, so the transient hazard happened.
Following description explains about said phenomenon using the timing chart showing in FIG.
9
. When the transient dv/dt signal flows to the line L
1
, at first the displacement currents flow through the parasitic capacity of the HNMOS transistor
2
,
3
and electric potentials at VR
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