Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1990-07-31
1993-05-04
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
Bad bit
365194, 328 62, G11C 700
Patent
active
052087760
ABSTRACT:
A pulse generation circuit is disclosed. The pulse generation circuit has a serially connected chain of delay elements, the first delay element for receiving an input pulse. It has a plurality of logic gates with each logic gate having one input coupled to the output of one delay element in the chain. The other input is coupled to the output of the next delay element in the chain. When the input pulse is received, the outputs of the logic gates form a plurality of non-overlapping pulses. Such a circuit is useful in a semiconductor memory device as a phase delay circuit.
REFERENCES:
patent: 4802127 (1989-01-01), Akaogi et al.
patent: 4985865 (1991-01-01), Houston
McAdams Hugh P.
Nasu Takumi
Bassuk Lawrence J.
Donaldson Richard L.
Holland Robby T.
Popek Joseph A.
Texas Instruments Incorporated
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