Pulse drive circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307450, 307296R, 307270, 307264, 365189, H03K 502, H03K 1708, H03K 1728, H03K 17284

Patent

active

047163135

ABSTRACT:
In order to drive a capacitance load at a high speed without an undesirably large increase in the circuit size, a driving arrangement is provided to charge the capacitance load in accordance with a limited voltage. A voltage limiter is coupled to a supply voltage providing a predetermined limited voltage. A pulse generator is coupled to receive the limited voltage and to provide output pulses which are, in turn, limited in accordance with the output voltage of the voltage limiter. A driver is coupled between the supply voltage and the capacitance load, and is controlled by the output pulses of the pulse generator. In this way, the capacitance load is charged through the driver in accordance with the limited voltage. Since the voltage limiter is not arranged along a series connection between the driver and the capacitance load, the internal equivalent resistance of the voltage limiter does not detrimentally influence the resistance along the series connection.

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Dingwall, "TTL to CMOS Buffer Circuit", RCA Technical Notes, No. 1114, pp. 1-3, Jun. 11, 1975.

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