Pull up circuit for sense lines in a semiconductor memory

Details Pull up circuit for sense lines in a semiconductor memory Pull up circuit for sense lines in a semiconductor memory

1988-09-30

1990-04-03

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

365210, 365205, G11C 700

Patent

active

049146319

ABSTRACT:
A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).

REFERENCES:
patent: 4578778 (1986-03-01), Aoyama
patent: 4679172 (1987-07-01), Kirsch et al.

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