Pull-up circuit for an input buffer

Details Pull-up circuit for an input buffer Pull-up circuit for an input buffer

2007-01-17

2009-11-03

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S009000, C326S033000, C327S313000

Reexamination Certificate

active

07612585

ABSTRACT:
An input buffer has a high voltage leg in parallel with a low voltage leg. The low voltage leg pulls up the pad when the pad voltage is below the power supply voltage. The high voltage leg remains off when the pad voltage is below the power supply. The low voltage leg is turned off when the pad voltage is above the power supply voltage. The high voltage leg is on when the pad voltage is above power supply voltage. A low voltage bias circuit and a high voltage bias circuit protect the transistors in the low and voltage legs when the pad voltage is above the power supply voltage. As a result, the pull-up circuit is high voltage tolerant and does not sink the current from pad.

REFERENCES:
patent: 5966026 (1999-10-01), Partovi et al.
patent: 6005413 (1999-12-01), Schmitt
patent: 6081132 (2000-06-01), Isbara
patent: 6313661 (2001-11-01), Hsu
patent: 6366122 (2002-04-01), Krishnamurthy et al.
patent: 6525559 (2003-02-01), Wu et al.
patent: 6674304 (2004-01-01), Matthews
patent: 6788107 (2004-09-01), Wang
patent: 7521966 (2009-04-01), Chong et al.
patent: 2005/0200381 (2005-09-01), Arai

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