Pseudostatic electronic memory

Details Pseudostatic electronic memory Pseudostatic electronic memory

1978-10-05

1980-05-13

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Data refresh

365149, G11C 700, G11C 1124

Patent

active

042031591

ABSTRACT:
An electronic memory is described which has only two transistors in each memory cell, but does not require that data processing be periodically interrupted to enable refreshing. It adds to a typical, single transistor cell dynamic memory one additional transistor per cell, and a duplication of the driving and sensing circuitry typically included in such a memory. The additional transistor in each cell provides access to the same for refreshing, which refreshing is accomplished by the additional driving and sensing circuitry at the very same time the memory is otherwise being accessed for data processing.

REFERENCES:
patent: 3922650 (1975-11-01), Schaffer
patent: 4112510 (1978-09-01), Baker
patent: 4122550 (1978-10-01), Caywood

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