Pseudomonolithic wafer scale module

Details Pseudomonolithic wafer scale module Pseudomonolithic wafer scale module

2000-07-18

2002-03-05

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S432000, C257S686000, C385S092000, C385S049000

Reexamination Certificate

active

06353264

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and, more specifically to a semiconductor device module that includes a plurality of integrated circuit devices formed by wafer-scale integration and oriented in a stacked configuration upon a heat dissipating base plate; and high-speed axial optical interconnects used to provide interconnections between the integrated circuit devices located at each stack level.
2. Description of the Prior Art
Conventionally, the manufacture of integrated circuits is accomplished by simultaneously fabricating a plurality of identical circuits on a single wafer. The wafer is later scribed into a plurality of chips that are separately packaged and later integrated into a larger system. For example, spacecraft avionics systems are large integrated systems having circuits built from conventional electronic chips and components. The chips are produced and packaged by many different manufacturers and because the packaged chips are substantially larger than the chips themselves, the circuits are typically much larger than is necessary to perform each circuit's intended function. These packaged chips may be placed into several spacecraft avionics units (black boxes) where each unit contains a specific function required for the given spacecraft system. More specifically, integrated circuits (ICs) on wafer board assemblies are enclosed inside black boxes where the circuitry contained within a particular black box communicates with other black boxes through limited bandwidth copper wires or optical fibers. As a result, connections between the black boxes are lossy and the number of spacecraft avionics units required for a particular system is typically large. The quantity, size, and interconnections required for such units necessitates spreading the units over a large physical area, thereby, preventing satellites or similar spacecraft from being compact and lightweight structures.
Wafer-scale integration has been described in the art as a method for alleviating individual chip packaging and integration by including all of the processing required for a particular function in a single integrated circuit formed on a single semi-conductor wafer. It has further been described as a means for meeting the demands of high-speed processing since, by including all of the processing means of a particular application in a single integrated circuit, short and high-speed interconnections may be formed. However, wafer-scale integration is not without its disadvantages, since defects due to the presence of impurities in the semiconductor crystal structure can occur and such defects can prevent individual circuit components located on the area of the defect from functioning properly. The larger the surface area of the wafer, the greater the number of defects; therefore, the ability to increase the wafer size to accommodate larger and larger systems is obviated in the absence of a defect-free wafer.
Various means of detecting and bypassing wafer defects have been utilized to mitigate the effects that such defects have on wafer-scale integrated circuits. Generally, the operative circuits or devices on a wafer are electrically isolated from the inoperative devices through the use of discretionary connections. For example, U.S. Pat. No. 5,514,884 discloses a method of using multiple identical blocks of addressable circuitry that are tested prior to interconnection to compensate for the defects in a wafer-size integrated circuit. The multiple identical blocks of circuit elements and multiple identical blocks of control logic are provided on a wafer where both the blocks of circuit elements and the blocks of control logic are small enough that blocks found to be defective can be discarded without significantly reducing the size of the device. U.S. Pat. No. 5,274,264 discloses a defect tolerant power distribution network for wafer-scale integrated circuits, and a method for detecting and removing short circuits from the network. Portions of the conductive lines in the power distribution network are fabricated with an area whose width is reduced relative to the remainder of the line. The amount of reduction in the line is sufficient to produce a hot spot in response to current flow to a short circuit that is located at an electrically downstream location on the line. Upon locating the hot spot as being associated with a specific circuit, the shorted circuit is removed from the remainder of the network by such means as laser cutting. U.S. Pat. Nos. 5,498,886 and 5,576,554 disclose forming a plurality of circuit modules on a wafer and grouping the modules into blocks arranged on a rectangular grid. An interconnect network including signal lines and power lines, each with built-in redundancy, surrounds each block. Each module and each segment of the interconnect network are tested and, by using fusible links, the defect-free segments of the interconnect network are connected to the functional circuit modules. U.S. Pat. No. 5,430,734 discloses an integrated circuit device that includes a wafer containing dynamically configurable gate arrays. The device provides a fault-tolerant design that addresses manufacturing defects by mapping all defective gate arrays and defective portions of each gate array on the wafer. Such defect mapping occurs during initial wafer testing following the wafer fabrication and the mapping information is later used to program the desired wafer functions to exclude defective portions of the wafer. U.S. Pat. No. 5,140,189 discloses creating externally formed connections to a wafer-scale semiconductor device to avoid wafer level defects located at various sites on the wafer. In particular, small external shorting blocks or patch circuits are utilized to define spare sites that may be used as replacement sites for defective primary sites. The patch circuit is used in combination with a decoder circuit that is coupled to a predetermined number of spare sites on a fully processed wafer-scale integrated (WSI) wafer. The decoder contains one enabling output for each spare site so that connections completed by the shorting block or patch circuit can assign a logical address for a defective primary site to a designated spare site. Control circuits also exist in the wafer to electrically remove one or more defective primary sites and to activate a required number of spare sites that operate as replacement sites for the defective primary sites. U.S. Pat. No. 5,084,838 discloses a plurality of integrated circuits mounted on a large-scale integrated circuit device that are each provided with a bypass circuit that selectively shorts input and output nodes in the corresponding unit integrated circuit. By selectively bringing the bypass circuit into a transfer state, all unit integrated circuits that are judged to be normal among a plurality of unit integrated circuits disposed along one row are coupled together.
To avoid testing individual circuits and manually connecting circuits to bypass defective circuit components, U.S. Pat. No. 5,287,345 discloses an array of interconnected node units formed as an integrated circuit on a semiconductor wafer for use in data handling, data processing or data storage. Each node unit includes a controlled switch for routing signal packets to destination node units whose addresses are included in the packets and also includes an automatic self-test function that, following satisfactory completion of the self-test, transmits a signal to adjacent node units that it is functioning properly. The controller of a node unit switch stores datum concerning which adjacent node units are defective and directs signal packets on paths around the defective node units.
Notwithstanding that wafer defect avoidance techniques, like those previously described, may be necessary to produce operative wafer-scale integrated circuits, such techniques may not, by themselves, be acceptable for wafer-scale integration that meets the demands of applications requiring increased processing speed

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