Pseudo-static single-ended cache cell

Details Pseudo-static single-ended cache cell Pseudo-static single-ended cache cell

2001-12-20

2003-09-09

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189050, C365S189080, C365S214000, C326S113000, C326S104000, C326S105000, C326S106000

Reexamination Certificate

active

06618316

ABSTRACT:

FIELD
Embodiments of the present invention relate to digital circuits, and more particularly, to cache memory cells.
BACKGROUND
As device technology scales to smaller dimensions, sub-threshold leakage current may present problems if circuits are not properly designed. The increase in sub-threshold leakage current may have a negative impact on circuit robustness, particularly for many single-ended caches in which each bit line is shared by a plurality of memory cells.
As an example, a portion of a cache circuit is shown in
FIG. 1
, where memory cell
102
is connected to local bit line
104
. In practice, there will be other local bit lines, as well as other memory cells connected to local bit line
104
, but for simplicity, only one local bit line is shown, and only one memory cell is shown connected to local bit line
104
. Memory cell
102
comprises cross-coupled static inverters
106
to store binary data, read-pass transistor
108
, and read-access transistor
110
. For simplicity, a write port is not shown.
During a pre-charge phase, clock signal &phgr; is LOW so that pullup transistor
114
is ON to charge local bit line
104
HIGH. The signal driving the gate of read-access transistor
110
, referred to as a read-select signal, is a dynamic signal, so that it is LOW during a pre-charge phase. During an evaluation phase, clock signal &phgr; is HIGH so that pullup transistor
114
is OFF.
Read operations are performed during an evaluation phase. For convenience, the data stored in a memory cell is taken as the logical value of the gate of the corresponding read-pass transistor, so that a logical “1” corresponds to a HIGH gate voltage and a logical “0” corresponds to a LOW gate voltage. Consider the case in which a read operation is performed on memory cell
102
. The read-select signal driving read-access transistor
110
is HIGH. Local bit line
104
is pulled LOW if memory cell
102
stores a logical “1”. If, however, the stored data is a logical “0”, then local bit line
104
will not be pulled LOW by memory cell
102
, in which case half-keeper
112
is designed to maintain local bit line
104
HIGH.
Consider a scenario in which all memory cells connected to local bit line
104
store a logical “1”. If during an evaluation phase no read operations are performed on the memory cells connected to local bit line
104
, then the cumulative effect of sub-threshold leakage current through each read-access transistor may discharge local bit line
104
LOW or close to LOW. Consequently, power must be expended to charge local bit line
104
HIGH during the next pre-charge phase, for otherwise an erroneous read operation may occur in the next evaluation phase.
Consider another scenario in which memory cell
102
stores a logical “0”, and all other memory cells connected to local bit line
104
store a logical “1”. Furthermore, suppose that during an evaluation phase a read operation is performed on memory cell
102
. The cumulative effect of sub-threshold leakage current in the other memory cells connected to local bit line
104
may be sufficient to pull local bit line
104
to LOW, or close enough to LOW, so that the stored data in memory cell
102
is incorrectly read as a logical “1”.
For some prior art circuits, half-keeper
112
is sized large enough so that local bit line
104
is not discharged by sub-threshold leakage current. However, a larger half-keeper increases contention when a local bit line is pulled LOW by a memory cell. This contention may degrade the performance of the cache. Furthermore, sub-threshold leakage current causes power to be expended to maintain local bit line
104
HIGH during a pre-charge phase, or to maintain local bit line
104
during an evaluation phase under the second scenario considered above.


REFERENCES:
patent: 4730274 (1988-03-01), Edwards
patent: 5339271 (1994-08-01), Tanagawa
patent: 5349558 (1994-09-01), Cleveland et al.
patent: 5488318 (1996-01-01), Vajapey et al.
patent: 5563842 (1996-10-01), Challa
patent: 5892726 (1999-04-01), Moon et al.
patent: 6081136 (2000-06-01), Khanna et al.
patent: 6094073 (2000-07-01), Campardo et al.
patent: 6144612 (2000-11-01), Numasawa
patent: 6362658 (2002-03-01), Pascucci
patent: 06103774 (1994-04-01), None

Affiliated with

Also associated with

Rating

Pseudo-static single-ended cache cell does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pseudo-static single-ended cache cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudo-static single-ended cache cell will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3008316