Pseudo-static random access memory

Details Pseudo-static random access memory Pseudo-static random access memory

1992-08-25

1994-02-22

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

365203, 365182, 36518911, G11C 1300

Patent

active

052894240

ABSTRACT:
In a pseudo-static random access memory of the invention, refresh operations are conducted in a normal mode and a self-refresh mode. The memory includes a plurality of bit-line pairs each having two bit lines, a precharge voltage generating circuit for precharging the plurality of bit-line pairs to a first potential level during a precharge period in the normal mode, the circuit being electrically connected to the plurality of bit-line pairs during the precharge period in the normal mode; and bit line discharge circuit for discharging the bit-line pairs during a precharge period in the self-refresh mode, thereby decreasing the potential level of the bit-line pairs to a second potential level which is below the first potential level.

REFERENCES:
patent: 5047985 (1991-09-01), Miyaja
patent: 5083047 (1992-01-01), Horie et al.

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