Pseudo-static memory device having internal self-refresh circuit

Details Pseudo-static memory device having internal self-refresh circuit Pseudo-static memory device having internal self-refresh circuit

1987-12-18

1989-02-28

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Data refresh

365230, G11C 700

Patent

active

048092339

ABSTRACT:
A pseudo-static memory device includes a memory cell array; a first access circuit for carrying out a sequential access to the word lines in the array to perform a refresh of cells; a second access circuit for bringing one of the word lines to an accessible state in response to an address signal; an access selection circuit for selecting either the first or the second circuit in accordance with an access precedence; a circuit for generating a control signal in response to a change in the address or a change in a level of an external clock; and a delay circuit for delaying the control signal by a predetermined time required for performing the refresh of cells.
The second access circuit performs an address access in response to the delayed control signal irrespective of the operation of the first access circuit, thereby providing a greater allowance for an address skew and a considerable allowance for a lag or lead of the timing of the application of the address signal.

REFERENCES:
patent: 4360903 (1982-11-01), Plachno et al.

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