Pseudo SRAM

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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Details

C365S154000

Reexamination Certificate

active

07957212

ABSTRACT:
A unit memory cell for use in a pseudo static random access memory (SRAM) includes a cell capacitor; a normal accessing transistor whose gate, drain and source are respectively connected to a normal accessing word line, a normal accessing bit line and a storage node of the cell capacitor; and a refresh accessing transistor whose gate, drain and source are respectively connected to a refresh accessing word line, a refresh accessing bit line and the storage node of the cell capacitor.

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patent: 1020040036556 (2004-04-01), None

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