Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-09
2002-11-05
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S329000, C257S330000, C257S331000
Reexamination Certificate
active
06476442
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to application Ser. No. 08/648,266 and application Ser. No. 08/649,747 each of which is being filed concurrently herewith and is incorporated herein by reference in its entirety.
FIELD OF THE INVENTION
This invention relates to voltage clamping devices and in particular to restricting current flows in PN diodes and MOS devices.
BACKGROUND OF THE INVENTION
A PN diode, when forward biased, is a minority carrier device and, as such, has a long recovery time compared to majority carrier devices. In many instances a PN diode is reverse-biased under normal operation but can become temporarily forward-biased due to transients in the circuit. During the time the PN diode is forward-biased, minority carriers are stored in the PN diode. In the event that the PN diode once again becomes reverse-biased, the stored minority carriers increase the reverse-recovery time of the PN diode (i.e., the time it takes a forward-biased diode to block a voltage applied in the reverse direction). Furthermore, once the minority carriers are removed under reverse-bias, a rapid voltage transient (i.e., large dv/dt) will occur, and voltage spikes beyond the supply voltages may also occur.
Since an parasitic PN diode (sometimes referred to as an “antiparallel” diode) is inherent in any MOSFET with a source-body short, the performance of any MOSFET can be degraded by the minority carriers of the PN diode. During Quadrant I operation (where the source terminal is connected to a lower voltage than the drain terminal), the parasitic diode is reverse-biased and will conduct no current. However if the MOSFET should enter Quadrant III operation (where the source terminal is connected to a higher voltage than the drain terminal) the parasitic diode will become forward-biased and will conduct a current with minority carriers. (Note. Unless otherwise specified herein, in MOSFETs where the body is shorted to a drain/source terminal, the shorted terminal will be referred to as the “source” and the non-shorted terminal will be referred to as the “drain”. In instances where the terms source and drain relate to their electrical function rather than their structure, the term “electrical source” or “electrical drain” will be used. For an N-channel MOSFET, the “electrical source” is more negative than the “electrical drain”. For a P-channel MOSFET, the reverse is-true.)
Several problems can result from the current through the parasitic diode. One problem is caused because the parasitic diode during conduction will begin to store charge, in the form of minority carriers, within the MOSFET. When the MOSFET returns to Quadrant I operation, the stored charge must be absorbed by the drain-to-source current of the MOSFET. Thus the switching time during the on-off transition and any associated power loss of the MOSFET will be increased. Furthermore, at the instant all the stored charge is absorbed a rapid voltage transition (i.e. large dv/dt) may occur. The large dv/dt in turn can cause snapback problems in the MOSFET (a form of undesirable bipolar transistor action), or trigger a latchup condition in an integrated circuit, where control of the device is lost.
If the MOSFET is part of an integrated circuit (IC), the current flowing through the parasitic diode may cause injection of minority carriers into the substrate of the IC. These minority carriers can travel through the substrate and cause various problems, such as latchup or snapback, in other devices throughout the IC.
Furthermore, the current through the parasitic diode can introduce charges into the IC that become majority carriers in different regions of the IC. In this situation voltage drops will occur in the IC creating a “ground bounce” situation in the IC (i.e., specialty varying ground potentials), which can cause latchup problems.
To avoid the problems caused by the parasitic diode of a MOSFET, the current which would pass through the parasitic diode of the MOSFET during Quadrant III operation can be shunted away from the parasitic diode by placing a shunting device in parallel with the diode. Moreover, a shunting device can also be used in parallel with any PN diode in order to prevent the problems caused by the minority carriers of a PN diode. Ideally, the shunting device should conduct no current when the PN diode is reverse-biased and turn on at a lower voltage than the PN diode when the PN diode is forward-biased. Due to the physical properties of silicon, silicon PN diodes have a turn-on voltage of 0.6 to 0.8 V. Within this range, a higher forward-bias voltage corresponds to higher current densities and more stored minority carrier charge. Therefore, the shunting device should have a turn-on voltage less than 0.6 V. Furthermore, for the parasitic diode of a MOSFET, the shunting device should also have a low recovery time so that the turn-off time of the MOSFET will not be degraded by the shunting device.
It is known in the art to use a Schottky diode as the shunting device. A Schottky diode is characterized by a low turn-on voltage (typically 0.2 to 0.3 volts), fast turn-off, and non-conductance when the Schottky diode is reverse-biased. Therefore, a Schottky diode can perform the functions of the shunting device.
However, to add Schottky diodes to an IC requires additional process steps. Specifically, to create a Schottky diode a metal-silicon barrier must be formed. In order to obtain the proper characteristics for the Schottky diode, the barrier metal will likely be different than the metal used in other process steps, such as metal ohmic contacts. These additional steps add cost and complexity to the IC.
Alternatively, discrete Schottky diodes can be connected in parallel with the MOSFET or PN diode of the IC in a multi-chip solution. However, in this type of connection there will exist various resistances, capacitances, and inductances within the connecting wires that may delay the Schottky diode's turn-on so that the parasitic or stand-alone PN diode will turn on before the Schottky diode. Furthermore, the use of discrete Schottky diodes is not ideal, since the clamping of the parasitic or stand-alone diode should be localized by placing the Schottky diode as close as possible to the parasitic or stand-alone diode.
Therefore, what is needed is a shunting device which can be manufactured in an IC without requiring additional process steps, and which has the properties of turn-on voltage lower than a silicon diode, a fast recovery time when switched from a forward-bias to reverse-bias condition, and non-conductance under reverse bias. Ideally, the shunting device could be merged into the power MOSFET itself without compromising the on-resistance or current density of the device.
SUMMARY OF THE INVENTION
This invention makes use of the “body effect” which occurs in a MOSFET when the PN junction between the body and the drain (electrical source) of the MOSFET is partially forward-biased. As a result of the body effect, the threshold voltage of the MOSFET is reduced, so that a relatively small voltage applied to the gate will cause a current to flow predominantly through the channel of the MOSFET, as compared to the parasitic diode that is formed at the body-drain junction. For example, with an N-channel MOSFET, if the body is given a small positive bias in relation to the drain (e.g., 0.05-0.6 V), the gate-to-source voltage V
gs
. that is necessary to turn the channel of the MOSFET on is reduced. With a P-channel MOSFET, if the body is given a small negative bias in relation to the drain, the V
gs
required to turn the channel on is likewise reduced in an absolute sense (i.e., a less negative V
gs
is required).
This type of arrangement may be constructed in several ways. If the MOSFET is fabricated as a four-terminal device, the body is properly biased in relation to the drain, and the gate is independently controlled (in an NMOS device, the drain being the terminal which is biased below the source). Alternatively, the MOSFET may be fabricated as a three-terminal device, with the body
Blattner Robert
Williams Richard K.
Fenty Jesse A.
Lee Eddie
Siliconix incorporated
Skjerven Morrill LLP
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