Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
2002-03-19
2003-12-16
Le, Don (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S119000
Reexamination Certificate
active
06664813
ABSTRACT:
FIELD OF INVENTION
The present invention generally relates to CMOS logic circuits, and more particularly to a pseudo-NMOS logic circuit with numerous inputs.
BACKGROUND
A pseudo-NMOS logic implemented in a CMOS circuit typically includes a load PFET (PMOS) with its gate tied to ground (GND), so that the load PFET is always ON. The source and the drain of the load PFET are connected between the supply voltage (VDD) and a “pulldown” NFET tree or circuit, respectively. A typical conventional pseudo-NMOS logic implemented in a CMOS circuit is shown in
FIG. 3
, where Z is the output node of the pseudo-NMOS logic. The pulldown NFET tree implements the desired equations of the pseudo-NMOS logic. A conventional pseudo-NMOS logic implementing a NOR equation, for example, is shown in FIG.
4
.
In a wide “fan-in” implementation of the pseudo-NMOS logic having numerous inputs to the pulldown tree, such as the NOR circuit shown in
FIG. 4
, “leakage” in the NFETs of the pulldown tree becomes a problem when the output at the node Z is high. A leakage occurs when there is undesirable current flow from source to drain even when the input voltage to the NFETs is zero or near zero. In other words, the NFETs do not act as a perfect switch. Power differential or noise at the inputs to the NFETs exacerbates the leakage problem, which results in noise being transmitted to other circuits that are connected to the output node Z of the pseudo-NMOS circuit.
The size (i.e., the width) of the load PFET can be increased to counter input noise and NFET leakage. In this manner the PFET becomes stronger (i.e., able to drive more current) so that there is less impact on the PFET by the leakage. However, this approach undesirably increases the voltage output level (VOL) when the NFETs are turned ON to produce a logical LOW value at the output Z. Alternatively, the size of the NFETs can be decreased. However, this method also results in increasing VOL.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, a pseudo-NMOS circuit includes a first PFET electrically connected between a power supply and an output node. An NFET circuit is connected between the output node and ground and has a plurality of inputs. A second PFET is electrically connected between the power supply and the output node, and has a gate which is controlled by a signal at the output node.
REFERENCES:
patent: 5831452 (1998-11-01), Nowak et al.
patent: 6060910 (2000-05-01), Inui
patent: 6130559 (2000-10-01), Balsara et al.
patent: 6172529 (2001-01-01), Klim et al.
patent: 6201415 (2001-03-01), Manglore
patent: 6208907 (2001-03-01), Durham et al.
patent: 6466057 (2002-10-01), Naffziger
Chang Edward
McCurdy Michael A
Hewlett--Packard Development Company, L.P.
Le Don
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