Pseudo master/slave decoupling of high speed bus...

Details Pseudo master/slave decoupling of high speed bus... Pseudo master/slave decoupling of high speed bus...

1999-08-05

2003-04-22

Gaffin, Jeffrey (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

Peripheral monitoring

C710S019000, C710S044000, C710S046000, C710S047000, C710S058000, C710S060000, C710S061000, C709S208000

Reexamination Certificate

active

06553434

ABSTRACT:

BACKGROUND
(1) Field of the Invention
The invention relates to a bus system. More specifically, the invention relates to satisfying timing constraints in high-speed bus systems.
(2) Background
One typical bus configuration is a system having a single master and a plurality of slaves. The master may, for example, go poll every slave to determine whether the slave has something to send to the master or whether the slave can accept something from the master. Depending on their responses to the polling, the master selects among the slaves to send or receive data. One existing bussing protocol that falls within this genre is the Utopia 2 protocol, as set forth in the Utopia Level 2, V 1.0 June 1995 (Utopia 2). Utopia 2 and subsequent revisions are referred to generically herein as “Utopia” protocols. The Utopia 2 system is a synchronous bus system in which the master communicates with the slaves by putting the address on the bus and then the slave having a corresponding address answers with its availability. Utopia 2 is broken down into two separate busses, a transmit bus and a receive bus. If the address is asserted on the receive bus, the answer indicates whether the slave has something to send to the master. If the address is asserted on the transmit bus, the answer indicates whether the slave is capable of receiving something from the master. There is a limited window after the assertion of the address within which the slave must answer. As clock speed increases, this window shrinks. For example, a 50 MHz clock implies a clock cycle of 20 ns, and therefore, a window for possible response of 20 ns. This means that the communication must pass between the master and the slave within 20 ns. In certain backplane environments, and any other time when the slave is relatively remote from the master, the propagation delay in the backplane coupled with other factors may cause the time budget for the communication to be exceeded. Typically, the total budget=clock to out+2 buffer delays+propagation delay+target setup+clock skew. At 50 MHz, this must be less than 20 ns for a valid transaction. On, for example, a 21″ backplane, the propagation delay alone may be eight ns, thereby absorbing 40% of the total timing budget. As a result, achieving synchronous bus speeds on the order of 50 MHz has been highly problematic in such systems.
BRIEF SUMMARY OF THE INVENTION
A system and method of decoupling timing in a high speed bus system is disclosed. A master/slave translator is coupled between a master device and a slave device. A pseudo slave of the master/slave translator responds to the master in a first timing protocol. A pseudo master of the master/slave translator masters the slave devices under a different timing protocol. The master/slave translator causes the master device to believe its communications with the slave device are occurring under the first protocol.


REFERENCES:
patent: 4885789 (1989-12-01), Burger et al.
patent: 5878234 (1999-03-01), Dutkiewicz et al.
patent: 6185643 (2001-02-01), Kirshtein et al.
patent: 6260082 (2001-07-01), Barry et al.
patent: 6327667 (2001-12-01), Hetherington et al.

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