Pseudo-dual port memory having a clock for each port

Details Pseudo-dual port memory having a clock for each port Pseudo-dual port memory having a clock for each port

2008-01-15

2008-01-15

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S154000

Reexamination Certificate

active

07319632

ABSTRACT:
A pseudo-dual port memory has a first port, a second port, and an array of six-transistor memory cells. A first memory access is initiated upon a rising edge of a first clock signal received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

REFERENCES:
patent: 5612923 (1997-03-01), Gibson et al.
patent: 5907508 (1999-05-01), Lattimore et al.
patent: 6862247 (2005-03-01), Yamazaki
patent: 6882562 (2005-04-01), Beucler

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