Pseudo-differential logic receiver

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor

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326 34, 326 83, A03K 19094

Patent

active

059949252

ABSTRACT:
A pseudo-differential receiver is described which includes a bias generator circuit portion for providing a bias signal to a receiver circuit portion. The bias generator includes first and second load devices for establishing bias voltages at first and second nodes and also includes a first CMOS inverter biased by and coupled between the first and second nodes. The input of the first inverter is coupled to a reference voltage and the output of the inverter provides a bias voltage which is fed back to the gates of the first and second load devices. The biasing conditions on the first and second nodes bias the first inverter such that the threshold voltage of the first CMOS inverter is equal to the reference voltage. The biasing signal is used to bias loading devices in the receiver circuit portion. The receiver circuit portion includes loading and inverter devices that are electrically matched to the loading and inverter devices in the bias generator circuit portion. As a result, the bias signal biases the receiver circuit loading devices such that the receiver circuit has the same threshold as the bias generator circuit which is equal to the input reference voltage coupled to the bias generator. The bias voltage provided by the bias generator can be used to bias other receiver circuit so as to minimize input receiver size and current in larger integrated circuit designs.

REFERENCES:
patent: 4255723 (1981-03-01), Ebihara
patent: 5376843 (1994-12-01), Tien et al.
patent: 5455520 (1995-10-01), Honda
patent: 5550487 (1996-08-01), Lyon
patent: 5900741 (1999-05-01), Roohparvar
Wang, et al., IEEE Journal of Solid-State Circuits, vol. 33, No. 4, Apr. 1988.

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