Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-02-22
2002-04-23
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S199000, C327S391000, C327S416000, C327S103000
Reexamination Certificate
active
06377084
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to integrated circuits. More particularly, it pertains to structures and methods for pseudo differential amplifiers.
BACKGROUND OF THE INVENTION
It is important to provide impedance matching on signal interconnection lines (i.e. transmission lines) to avoid reflections and ringing on the transmission lines at high data rates. Many different techniques have been utilized in CMOS technology to reduce reflections and ringing on high speed interconnections, including limiting slew rates on signals, resistor terminations, diffused resistor terminations, using only non-resonant lengths on the transmission lines and using controlled impedance drivers. One technique for providing impedance matched terminations is to use current sense amplifiers and current mode sensing. In this technique, the current sense amplifier can be designed to provide a lower input impedance than the conventional voltage sense amplifiers which employ voltage sensing of the transmission line signals.
Presently, most CMOS integrated circuit interconnections rely on the transmission of a voltage step or signal from one location to another. The driver may simply be a CMOS inverter with a passive pull up load resistor and the receiver a simple CMOS amplifier, differential amplifier or comparator. The CMOS receiver presents a high impedance termination or load to the interconnection line. This fact is problematic for several identifiable reasons. In example, the high impedance termination is troublesome because the switching time response or signal delay is determined mainly by the ability of the driver to charge up the capacitance of the line and the load capacitance. Also, the interconnection line is not terminated by its characteristic impedance resulting in reflections and ringing. Thus, large noise voltages may be induced on the signal transmission line due to capacitive coupling and large voltage switching on adjacent lines. The result is that the noise voltage can be a large fraction of the signal voltage.
The transmission of voltage step signals works well if the interconnection transmission line is short so that the stray capacitance of the line is less. However, in longer low impedance transmission lines, such as those which exist on most CMOS integrated circuits, the noise voltage presents a difficult problem. These longer low impedance transmission lines are in fact more amenable to current signaling. These longer transmission lines may be on the CMOS integrated circuit itself, an interconnection line between integrated circuits mounted in a module as for instance a memory module, an interposer upon which these integrated circuits are mounted, or on a printed circuit board upon which the integrated circuits are mounted.
Independent of whether voltage signals or current-mode signals are employed two different types of interconnections exist, the first type includes single sided/single ended interconnections and the second type includes differential interconnections. Differential interconnections are often desirable in that they reduce common mode noise. However, differential interconnections require two interconnection transmission lines and, in I/O applications, they require twice as many input/output pads and packaging pins which is a problem in some applications. The requirement of two interconnection transmission lines creates twice as much crowding on the precious chip surface area available in certain CMOS applications. Single sided/single ended pseudo differential interconnections have some of the advantages of differential interconnections, like power supply noise rejection. Single sided/single ended pseudo differential interconnections use a single transmission line interconnection.
In the “quasi-differential” amplifier, a single transmission line interconnection is utilized and one input of the voltage sense amplifier driven with a reference potential. The “quasi-differential” technique, and with voltage sensing on a terminated line has been used in 400 Mbs CMOS systems.
FIG. 1
provided a schematic for a conventional “pseudo-differential” amplifier. In the “pseudo-differential” amplifier technique one side of the different type of voltage sense amplifier is driven with a combination of ground potential and a reference potential. Unfortunately, achieving high data rates is difficult with single-ended or unbalanced signal transmission lines at high frequencies because of large amount of noise is generated in the interconnection system including crosstalk and radiation in backpanes, connectors and cables.
FIG. 2
provides an illustration of the conventional differential current sense amplifier. This conventional current sense amplifier, receiving fully differential input signals, can respond more rapidly than those single ended/single sided amplifiers mentioned above. Also, the fully differential sense amplifier has lower power constraints and can be driven with a small 0.5 mA input signal on the input transmission lines. The conventional differential current sense amplifier is not very responsive to single sided or single ended input signals where one side, or input, is driven with a reference current signal, e.g. zero Amperes and the other input is used in an attempt to detect a current signal. When used in such a manner the response of the current sense amplifier with a single sided input is very poor. There is simply not enough gain and feedback in the positive feedback latch to result in a large output signal for a 1 milliampere (mA) input signal. Instead a larger 5 mA input signal is required which places greater power demands on the overall CMOS circuit.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop improved single ended or “pseudo differential” amplifiers which can be fabricated according to a conventional CMOS process and provide responsive performance for current signal inputs of 2.0 mA and lower.
SUMMARY OF THE INVENTION
The above mentioned problems with CMOS integrated circuits as well as other problems are addressed by the present invention. Novel single ended receivers and “pseudo differential” amplifiers are provided which conserve scarce chip surface area yet still provide fast response times in a low power CMOS environment.
A first embodiment includes a single ended receiver. The single ended receiver includes a pair of cross coupled inverters. Each of the inverters includes a pair of output transmission lines. Each one of the pair of output transmission lines is coupled to a drain region on each one of the pair of cross coupled inverters. A single signal input node coupled to a source region for one of the pair of cross coupled inverters. The single signal input node is further coupled to a current mirror such that the single ended receiver is able to convert a single ended input current received at the single signal input node into a differential input signal. In this manner, the single ended receiver is able to latch a voltage output signal on the pair of output transmission lines when a current signal of 2.0 milliampere (mA) or less is received at the single signal input node.
A second embodiment includes a pseudo differential amplifier. The pseudo differential amplifier includes a pair of cross coupled transistors. The pseudo differential amplifier includes a pair of signal output nodes. Each one of the pair of signal output nodes is coupled to a drain region for each transistor in the cross coupled pair of transistors. Each one of the pair of signal output nodes is further coupled to a gate of the other transistor in the cross coupled pair of transistors. A single signal input node is coupled to a source region for one of the transistors in the pair of cross coupled transistors. The single signal input node is further coupled to a current mirror such that the pseudo differential amplifier is able to convert a single ended input current received at the sin
Englund Terry L.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
Wells Kenneth B.
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