Pseudo-anding in dynamic logic circuits

Details Pseudo-anding in dynamic logic circuits Pseudo-anding in dynamic logic circuits

1999-06-10

2002-01-15

Phan, Trong (Department: 2818)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06339835

ABSTRACT:

TECHNICAL FIELD
This invention relates generally to digital logic, and more specifically, to a network of logic gates, such as dynamic logic gates incorporating foot devices.
BACKGROUND INFORMATION
The use of dynamic logic is an efficient way of increasing circuit speed and reducing (lie area of integrated circuitry. Many dynamic circuit schemes have been described which share common basic features. The basic dynamic gate, shown in
FIG. 1
, includes a logic structure whose output node is precharged to VDD by a p-type transistor (the“precharge” transistor) and conditionally discharged to ground by an n-type transistor (the“evaluate” transistor). The precharge and evaluate transistors are typically connected to a single phase clock. During the precharge phase, the clock is low and the output node is precharged to VDD. At the completion of the precharge phase, the clock goes high and the path to VDD is turned off while the path to ground is conditionally turned on. In this evaluate phase, depending on the state of the data inputs, the output will either be at a high level or will be pulled down.
This dynamic logic is advantageous in that it generally requires less transistors than static logic. Note, there is often an inverter employed at the output in order to cascade such dynamic logic circuits, as shown in FIG.
2
.
However, when many of these circuits are cascaded, delays in propagating the signal through the cascaded blocks can mount. Therefore, there is a need in the art for faster dynamic logic circuitry.
SUMMARY OF THE INVENTION
A typical domino logic circuit has a foot device, which is the n-type evaluate transistor coupled between the n-type logic circuitry receiving the data inputs and the ground potential. This sequential arrangement implements protection from accidental discharge of the precharge node (which would result in an invalid evaluation). Proper evaluation occurs when the data is 1 and the clock is 1. This AND function provides an opportunity to move full domino AND blocks fed by full domino books of any type to the clock input of the source book. This makes the source book act like a pseudo-clocked book with a reset that must propagate from the AND block moved to its clock input. If the AND block were on the critical path, a complete stage of logic can be removed.
By employing pseudo-ANDing, improvements in speed can be realized with various circuit configurations.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.


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