Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2011-03-01
2011-03-01
Song, Jasmine (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S134000, C711S135000, C711S151000, C711S158000, C711S159000
Reexamination Certificate
active
07899994
ABSTRACT:
In one embodiment, the present invention includes a method for associating a first priority indicator with first data stored in a first entry of a cache memory to indicate a priority level of the first data, and updating a count value associated with the first priority indicator. The count value may then be used in determining an appropriate cache line for eviction. Other embodiments are described and claimed.
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patent: 6292871 (2001-09-01), Fuente
patent: 7242692 (2007-07-01), Wu et al.
patent: 2004/0260880 (2004-12-01), Shannon et al.
patent: 2005/0114605 (2005-05-01), Iyer
U.S. Appl. No. 11/087,916, filed Mar. 22, 2005, entitled “A Cache Eviction Technique For Reducing Cache Eviction Traffic” by Christopher J. Shannon, et al.
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U.S. Appl. No. 11/503,777, filed Aug. 14, 2006, entitled, “A Selectively Inclusive Cache Architecture,” by Ravishankar Iyer, Li Zhao, Srihari Makineni and Donald Newell.
U.S. Appl. No. 11/513,554, filed Aug. 31, 2006, entitled, “Selective Storage Of Data In Levels Of A Cache Memory,” by Srihari Makineni, Jaideep Moses, Ravishankar Iyer, Ramesh Illikkal, Donald Newell and Li Zhao.
Illikkal Ramesh
Iyer Ravishankar
Makineni Srihari
Newell Donald
Zhao Li
Intel Corporation
Song Jasmine
Trop Pruner & Hu P.C.
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