Providing multiple memory controllers on a memory bus

Details Providing multiple memory controllers on a memory bus Providing multiple memory controllers on a memory bus

2005-03-15

2005-03-15

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S117000, C710S045000, C710S027000, C710S028000, C711S157000

Reexamination Certificate

active

06868486

ABSTRACT:
A system comprises a plurality of memory controllers connected to a memory bus. Each memory controller is able to generate memory requests on the memory bus according to a predetermined priority scheme. One priority scheme is a time slot priority scheme, and another priority scheme is a request-select priority scheme. The plurality of memory controllers are able to monitor memory requests generated by another memory controller in performing memory-related actions, such as memory requests (read or write), read-modify-write transaction, and cache coherency actions. In one arrangement, the memory bus is a Rambus channel.

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