Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-07-31
2010-11-02
Song, Jasmine (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S141000, C711S144000
Reexamination Certificate
active
07827357
ABSTRACT:
In one embodiment, the present invention includes a method for receiving requested data from a system interconnect interface in a first scalability agent of a multi-core processor including a plurality of core-cache clusters, storing the requested data in a line of a local cache of a first core-cache cluster including a requester core, and updating a cluster field and a core field in a vector of a tag array for the line. Other embodiments are described and claimed.
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U.S. Appl. No. 11/526,431, filed Sep. 25, 2006, entitled, “Adaptively Reducing Memory Latency In A System,” by Krishnakanth Sistla.
U.S. Appl. No. 11/606,347, filed Nov. 29, 2006, entitled “Conflict Detection And Resolution In A Multi Core-Cache Domain For A Chip Multi-Processor Employing Scalability Agent Architecture,” by Krishnakanth Sistla.
U.S. Appl. No. 11/605,636, filed Nov. 29, 2006, entitled “System And Method For Aggregating Core-Cache Clusters In Order To Produce Multi-Core Processors,” by Krishnakanth Sistla.
Intel Corporation
Song Jasmine
Trop Pruner & Hu P.C.
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