Provably correct storage arrays

Details Provably correct storage arrays Provably correct storage arrays

1999-08-19

2001-08-21

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C257S390000, C257S903000, C365S189020, C365S201000, C365S233100, C714S726000

Reexamination Certificate

active

06279144

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to design of provably correct arrays in complex logic and memory systems implemented in very large scale integrated (VLSI) circuits and, more particularly, to a hardware design technique that allows checking the design system language (DSL) specification of large macros with embedded arrays and registers.
2. Background Description
As the number of transistors used for complex logic and memory increases on a central processing unit (CPU) chip, the verification of intended functionality versus the actual functionality becomes a major task. To illustrate this point, many top level circuits as well individual circuits need to be evaluated with respect to static function, timing, testability of scan chain and manufacturability. As a result, a complete verification of logic and memory on a CPU chip is a necessity for low development cost and short design delivery cycles.
In the verification process, user-defined functions are checked at gate or transistor levels. The user defined functions are coded in Boolean algebra. The checking is done from top to bottom, which is termed as hierarchical.
The functional behavior of a high level system (e.g., a CPU chip) is validated by first modeling at an abstract level. This abstract level is simulated using a predesigned environment, such as running software applications or running a random set of processor instructions. Once the desired performance is achieved, the abstract model becomes the definition of the intended system function. This is often referred to as the “golden model”.
The golden model can be synthesized to achieve gate levels description of the intended function. Conventionally, the synthesis is done automatically. The automation may limit the possible implementation of styles as it can grab fixed cells from the designated libraries. This may not result in optimization of area, timing and power. However, the synthesis maintains the functionality of the abstract specification, provided that the algorithms applied are correct. As a result, the functional verification is performed on the final design to confirm the validity of the synthesis algorithms.
Normally, the synthesis procedure is adopted for random logic especially when the synthesis rules are easily available (e.g., libraries, timing, pin information, etc.). It is easier to create libraries for static circuits. However, many times these limit the performance. As a result, a combination of dynamic and static circuits are used in to improve performance. In addition, circuits are tuned to the performance, and custom layouts to reduce area and power are heavily used. This is typically termed as custom or semi-custom (mixed static and dynamic) design. The custom design process is normally done independent of the “golden model”. As a result, a separate functional verification step for the final implementation is very crucial. There are two approaches to custom circuit verification.
In the first approach, the switch level representation of complementary metal oxide semiconductor (CMOS) circuits is stimulated using the system level stimuli. The smaller granularity of this model causes a significant increase in simulation complexity. This reduces total number of patterns which in turn reduce the verification coverage. To resolve this problem, gate level model is abstracted from the transistor representation and by using hardware accelerators for switch level simulation. In spite of these developments these repeated functional simulations on the circuit level is highly time-intensive and difficult for user friendly applications.
A method to formally verify memory circuits based on the second approach compares transistor level logic (decoder, resets etc.) and memory and high level specification. Even though the specification is listed “fully functional”, at the transistor level design may result in errors due to limitations on the test pattern coverages. Thus, by checking transistor level design with formal specification can produce robust design methodology. The goal here is to achieve substantial pattern coverage across the memory design.
The Present Problem
The verification of a memory unit is done by partitioning logic and array on the chip, since the verification system can not handle large systems as one entity. It is important to have a proper partitioning of the given memory system without blowing the verification environment. During the course of the design cycle, the high level model can go through some changes which may invalidate the transistor level representation. Also, when the memory contains some logic along with it, the verification of such a circuit becomes very difficult as latches or memory elements can not be modeled by Boolean expressions.
An example of a logic and memory circuit used in a microprocessor is given in FIG.
1
. See, for example, U.S. Pat. No. 5,617,047 to W. H. Henkels et al. and U.S. Pat. No. 5,481,495 to W. H. Henkels et al., both assigned to the assignee of this invention. The description pertains to a register file with m word lines and n bit lines. The logic in
FIG. 1
is denoted by write and read decoders and represented by blocks WRITE_A&B, READ_A, READ_B and READ_S respectively. A, B and S denote the port names. The addresses to the write decoder are given by WAA<0:4>, WBA<0:4>, WATS(Write address timing signal), WEA(Write Enable for port A) and WEB(Write Enable for port B). Addresses to the read ports are denoted by A<0:4> and their complements by AC<0:4>. These addresses create (in this case m word lines=32) word lines and read the appropriate data written in the array by triggering write word lines. In a conventional architecture, memory array A
3
in
FIG. 1
is organized to optimize the layout performance in a vertically bit-sliced way, as shown in FIG.
2
. That is, a single write bit line would be written in a latch by triggering the pass gates by write word line. Then whatever is held in the latch is read by triggering the read word line and the data is transmitted across the read bit line to create a signal on the read bit line. Most of the time, the read word lines are banked into a desired number to create a pitch matched circuitry. In a vertical bit sliced fashion, the single read bit line is multiplexed with read word lines which are banked in a desired group. The output of such several multiplexers is then logically ORed to give the desired signal bit output.
If the logic of the design system language (DSL) written for verification of such a vertical bit-sliced organization is used to simulate the whole macro containing the array, then the simulation model becomes five times larger, and simulation is five times slower since it is bit level rather word level.
The following example illustrates the present problem more clearly. For a register file with m=32 words by n=64 bits, vertical slicing results in 32×64=2048 latch elements (1-bit wide) being modeled. This results in a much larger simulation model and much slower simulation run times. The simulation modeling of each latch element requires a certain amount of overhead that is independent of the width. Horizontal slicing results in 32 latch elements (64 bits wide) being modeled. Since the number of latch elements is reduced, the model size is smaller and the simulation run time is faster.
Viewing simulation output is also complicated by vertical slicing. Vertical slicing causes each bit to have a unique facility name. Horizontal slicing allows an entire word (64 bits) to be accessed by a single facility name. Thus, it is difficult to debug the logic since only the register bits are accessible in the main simulation model and not the registers as a whole, and the vertical bit slicing makes “verification” process blow up in an exponential order of magnitude. In short, verification of the combination of logic and memory circuit puts constraints on the computational time and increases the complexity.
SUMMARY OF THE INVENTION

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