Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-07-12
2002-12-31
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C361S600000
Reexamination Certificate
active
06502221
ABSTRACT:
FIELD
The present invention relates to a prototype development system. In particular, the invention is used by engineers to quickly and accurately develop a electronic prototype that is designed to represent a target circuit such as a microprocessor.
BACKGROUND
Prototype construction has been used by many electronics companies to improve their circuit designs before investing large sums of money in fabricating integrated circuits. One conventional technique of verifying a circuit is a software simulation. In this technique, the circuit is portrayed by software in a computer and the computer performs all the steps necessary to simulate operation of the circuit. This technique is time consuming both in that the computer must be programmed for each of the circuit elements (sometimes taken from a library) and that the general purpose computer must simulate all the signals internal to the simulated circuit. A high performance computer can simulate the clock rate of the circuit at only a small fraction of the actual circuit operational clock, for example, {fraction (1/1,000,000)} of real time.
Alternatively, conventional emulation techniques can be used that more accurately portray the operational circuit. A conventional emulation technique is described in U.S. Pat. No. 5,036,473. This type of emulator employs programmable gate arrays (PGAs) that are programmed to perform the functions of the desired circuit. The PGAs are coupled to one another by a cross-bar switch network that is controlled with a switch controller. In order to emulate the desired circuit, both the PGAs need to be programmed as well as the switch network. The switch network programming is generally difficult because it requires that the connections between the PGAs be programmed for specific connections at specific times, while adhering to a myriad of constraints. This task can easily take an engineer a week or more to write. A high performance emulator can emulate the clock rate of the circuit by only a small fraction of the actual circuit operational clock primarily due to the programmable interconnect.
Both the software technique and the emulator technique suffer from the time required to either simulate or emulate the design. For example, a Pentium class processor has in excess of 8 million transistors (about 2 million gates), and the clock rate of a Pentium class processor can be in excess of 500 Mhz. A high performance computer can only clock the simulated design at a rate of approximately 500 Hz. As a result, full simulation of the design could take months or years. A high performance emulator may be able to clock the emulated design at a rate of approximately 500 KHz. As a result, full simulation of the design could take weeks or months. Moreover, if a problem is discovered in the design or in the simulation or emulation, additional weeks or months are spent fixing and re-simulating or re-emulating the design. This is a very expensive and time-consuming process.
An alternative to simulation and emulation is a custom prototype. This is an expensive and time-consuming task since it means starting from scratch for each design. The engineer constructs a custom prototype using programmable logic and a dedicated target board. The custom prototype provides the most realistic circuit and can simulate the desired circuit the fastest since the custom prototype employs dedicated processors and interface components. However, if a modification is desired (e.g., due to an error or design change), modifying the custom prototype can be expensive and time-consuming, if not impossible.
Accordingly, a limitation of conventional simulation and emulation techniques are that they are expensive and slow. Additionally, conventional emulators are difficult to program, and any modifications made to the design cause substantial circuit modification and re-programming. Moreover, a limitation to the custom prototype is that modification is expensive, if not impossible.
Therefore, a goal of the invention is to overcome the identified limitations and to provide a cost-effective technique for developing a prototype that combines the advantages of the custom prototype speed with the flexibility of the re-programmable emulators.
SUMMARY
The invention overcomes the identified problems and provides a prototype system that combines the advantages of the custom prototype speed with the flexibility of the re-programmable emulators. An exemplary embodiment of a prototype development apparatus includes a logic board (LB) including a plurality of integrated circuit (IC) sites each adapted to receive an IC, logic traces coupled to each of the IC sites, and a plurality of logic board connector sites (LBCSs) configured to provide access to a number of the logic traces and each adapted to receive a connector. Additionally, a mezzanine board (MB) has a plurality of mezzanine board connector sites (MBCSs) each adapted to receive a connector and configured to provide access to a number of mezzanine traces interconnecting the MBCSs. The MB board is coupled to the LB and a portion of the logic traces are coupled to a portion of the mezzanine traces.
In the exemplary embodiment, the MB does not have any active components.
This is because in this embodiment, the MB is solely configured to connect the pins of the connector sites. However, additional embodiments employ components on a portion of the MB.
In another embodiment, the integrated circuits (ICs) are programmable gate arrays (PGAs) that can be re-programmed. A computer is used to generate a netlist representative of a target circuit. The computer divides the netlist into first portions to be programmed into the PGAs and second portions to interconnect the PGAs. The computer then programs the first portions into the PGAs. A mezzanine board is fabricated based on the second portions. Finally, the LB and the MB are coupled together such that the target circuit is constructed from both the LB and the MB.
In practice, the LB contains re-programmable PGAs and the MB contains a dedicated interconnect structure (the mezzanine traces). With these two boards coupled to one another, flexibility is achieved because the PGAs are re-programmable and speed is achieved because the interconnect structure is dedicated traces. Moreover, the interconnect structure can be quickly modified by re-fabrication and replacement of the MB.
Advantages of the present invention include providing a cost-effective technique for developing a prototype that combines the advantages of the custom prototype speed with the flexibility of the re-programmable emulators.
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Hasslen, III Robert J.
Martinez Fernando G.
Nicolino, Jr. Sam J.
Vogel Ernest P.
Niebling John F.
Nvidia Corporation
Silicon Valley IP Group
Whitmore Stacy
Zilka Kevin J.
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