Protocol for communication with dynamic memory

Details Protocol for communication with dynamic memory Protocol for communication with dynamic memory

2001-05-29

2002-10-22

Wiley, David (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

C710S107000

Reexamination Certificate

active

06470405

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to dynamic random access memory (DRAM), and more specifically, to a method and apparatus for controlling data transfers to and from a dynamic random access memory.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM) components, such as those illustrated in
FIG. 1A
, provide an inexpensive solid-state storage technology for today's computer systems. Digital information is maintained in the form of a charge stored on a two-dimensional array of capacitors. One such capacitor is illustrated in FIG.
1
B.
FIG. 2
illustrates a prior art memory system including DRAM with the corresponding control, address and data wires which connect the DRAM to the processor or memory controller component. In synchronous DRAMs, a write access is initiated by transmitting a row address on the address wires and by transmitting row address strobe (RAS) signal. This causes the desired row to be sensed and loaded by the column amplifiers. The column address is transmitted on the address wires and the column address strobe (CAS) signal is transmitted along with the first word of the write data WData(a,1). The data word is then received by the DRAM and written into the column amplifiers at the specified column address. This step can be repeated “n” times in the currently loaded row before a new row is sensed and loaded. Before a new row is sensed, the old row must be restored back to the memory core and the bit lines of the DRAM precharged.
FIG. 3A
illustrates synchronous write timing. In the figure, a, b . . . represent a row address; 1, 2 . . . n represent a column address, WData [row, col] represents the DRAM address of data words, the row address strobe (RAS) is a control signal for initiating a sense operation, and WRITE(CAS) initiates the write operation on the column amplifiers. In the present example, the row column address delay timing parameter is equal to two clock cycles. After the row address is asserted at the first clock cycle, column addresses and write data are asserted after the delay to write the data into the DRAM array.
FIG. 3B
illustrates synchronous read timing. A processor initiates a read access by transmitting a row address on the address wires and by transmitting the row address strobe (RAS) signal. This causes the desired row to be sensed by the column amplifiers. The column address is then transmitted on the address wire and the column address strobe (CAS) signal is transmitted. The first word of the read data RData (a,1) is then transmitted by the DRAM and received by the processor. This step can be repeated “n” times in the currently loaded row before a new row is sensed and loaded. Before a new row is sensed, the old row must be restored back to the memory array.
Various attempts have been made to improve the performance of conventional DRAMs. Such attempts have resulted in DRAM architectures that deviate in varying degrees from conventional DRAM architectures. Various alternative DRAM architectures are described in detail in NEW DRAM TECHNOLOGIES, by Steven A. Przybylski, published by MicroDesign Resources, Sebastopol, Calif. (1994). Some of those architectures are generally described below.
EXTENDED DATA-OUT DRAMS
The prior art includes Extended Data-Out (EDO) memory systems. In EDO DRAMs, the output buffer is controlled by signals applied to output enable (OE) and column address stobe (CAS) control lines. In general, data remains valid at the output of an EDO DRAM longer than it does for conventional DRAMs. Because the data remains valid longer, the transfer of the data to the latch in the memory controller can be overlapped with the next column precharge. As a result, burst transfers can be performed in fewer clock cycles.
SYNCHRONOUS DRAMS
The prior art also includes Synchronous DRAM (SDRAM) memory systems. The interface of an SDRAM includes a multiplexed address bus and a high-speed clock. The high speed clock is used to synchronize the flow of addresses, data, and control on and off the DRAM, and to facilitate pipelining of operations. All address, data and control inputs are latched on the rising edge of the clock. Outputs change after the rising edge of the clock. SDRAMs typically contain a mode register. The mode register may be loaded with values which control certain operational parameters. For example, the mode register may contain a burst length value, a burst type value, and a latency mode value. The burst length value determines the length of the data bursts that the DRAM will perform. The burst type value determines the ordering of the data sent in the bursts. Typical burst orders include sequential and sub-block ordered. The latency mode value determines the number of clock cycles between a column address and the data appearing on the data bus. The appropriate value for this time interval depends largely on the operating frequency of the SDRAM. Since the SDRAM cannot detect the operating frequency, the latency mode value is programmable by a user.
REQUEST ORIENTED DRAM SYSTEMS
The prior art also includes memory systems in which data transfer operations are performed by DRAMs in response to transfer requests issued to the DRAMs by a controller. Referring to
FIG. 4
, it illustrates a memory system in which data transfers are made in response to transfer requests. The request packet format is designed for use on a high speed multiplexed bus for communicating between master devices, such as processors, and slave devices, such as memories. The bus carries substantially all address, data, and control information needed by the master devices for communication with the slave devices coupled to the bus. The bus architecture includes the following signal transmission lines: BusCtl, BusData [8:0], BusEnable, as well as clock signal lines and power and ground lines. These lines are connected in parallel to each device.
The processors communicate with the DRAMs to read and write data to the memory. The processors form request packets which are communicated to the DRAMs by transmitting the bits on predetermined transmission lines at a predetermined time sequence (i.e. at predetermined clock cycles). The bus interface of the DRAM receiver processes the information received to determine the type of memory request and the number of bytes of the operation. The DRAMs then perform the memory operation indicated by the request packet.
FIG. 5
illustrates command control information
500
that is sent in a data transfer request according to a prior art protocol. In the illustrated example, the command control information
500
is sent over a BusCtl line and a nine-bit data bus (BusData[8:0]) in six clock cycles. The command control information
500
includes groups of bits
501
,
502
,
504
,
506
and
508
that constitute an address, an operation code consisting of six bits
510
,
512
,
514
,
516
,
518
and
520
, and groups of bits
522
,
524
and
528
that specify a count. The address identified in the command control information
500
specifies the target DRAM and the beginning location within the DRAM of the data on which the operation is to be performed. The count identified in the command control information
500
specifies the amount of information on which the operation is to be performed.
SUMMARY AND OBJECTS OF THE INVENTION
One object of the present invention is to provide a mechanism to decouple control timing from data timing.
Another object of the present invention is to provide mechanisms that use minimal bandwidth to determine data dining while minimizing the latency from signaling that the data transfer should terminate to the transmission of the final data packet.
Another object of the present invention is to provide mechanisms for arbitrarily long data transfers following a command. This may include simultaneous provision of a new column address for each data packet transferred.
Another object of the present invention is to provide a means to signal simultaneously with termination of the data transfer that a precharge operation should be performed.

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